diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2015-08-27 22:49:43 +0200 |
|---|---|---|
| committer | Linaro Code Review <review@review.linaro.org> | 2015-09-09 12:00:04 +0000 |
| commit | 1ae867da115fda78ceddfe73c635f778040391b5 (patch) | |
| tree | fc212022ef9ed4333787f80efb873e934449a480 /gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c | |
| parent | b52eecc1c264ee352d36de042af9301afa517335 (diff) | |
gcc/testsuite/
Backport from trunk r223508.
2015-05-21 Sandra Loosemore <sandra@codesourcery.com>
* gcc.target/arm/simd/simd.exp: Skip all tests if no arm_neon_ok
effective target support. If no arm_neon_hw support, do not attempt
to execute the tests; only compile them.
* gcc.target/arm/simd/vextf32_1.c: Remove explicit "dg-do run"
and "dg-require-effective-target arm_neon_ok".
* gcc.target/arm/simd/vextp16_1.c: Likewise.
* gcc.target/arm/simd/vextp64_1.c: Likewise.
* gcc.target/arm/simd/vextp8_1.c: Likewise.
* gcc.target/arm/simd/vextQf32_1.c: Likewise.
* gcc.target/arm/simd/vextQp16_1.c: Likewise.
* gcc.target/arm/simd/vextQp64_1.c: Likewise.
* gcc.target/arm/simd/vextQp8_1.c: Likewise.
* gcc.target/arm/simd/vextQs16_1.c: Likewise.
* gcc.target/arm/simd/vextQs32_1.c: Likewise.
* gcc.target/arm/simd/vextQs64_1.c: Likewise.
* gcc.target/arm/simd/vextQs8_1.c: Likewise.
* gcc.target/arm/simd/vextQu16_1.c: Likewise.
* gcc.target/arm/simd/vextQu32_1.c: Likewise.
* gcc.target/arm/simd/vextQu64_1.c: Likewise.
* gcc.target/arm/simd/vextQu8_1.c: Likewise.
* gcc.target/arm/simd/vexts16_1.c: Likewise.
* gcc.target/arm/simd/vexts32_1.c: Likewise.
* gcc.target/arm/simd/vexts64_1.c: Likewise.
* gcc.target/arm/simd/vexts8_1.c: Likewise.
* gcc.target/arm/simd/vextu16_1.c: Likewise.
* gcc.target/arm/simd/vextu32_1.c: Likewise.
* gcc.target/arm/simd/vextu64_1.c: Likewise.
* gcc.target/arm/simd/vextu8_1.c: Likewise.
* gcc.target/arm/simd/vrev16p8_1.c: Likewise.
* gcc.target/arm/simd/vrev16qp8_1.c: Likewise.
* gcc.target/arm/simd/vrev16qs8_1.c: Likewise.
* gcc.target/arm/simd/vrev16qu8_1.c: Likewise.
* gcc.target/arm/simd/vrev16s8_1.c: Likewise.
* gcc.target/arm/simd/vrev16u8_1.c: Likewise.
* gcc.target/arm/simd/vrev32p16_1.c: Likewise.
* gcc.target/arm/simd/vrev32p8_1.c: Likewise.
* gcc.target/arm/simd/vrev32qp16_1.c: Likewise.
* gcc.target/arm/simd/vrev32qp8_1.c: Likewise.
* gcc.target/arm/simd/vrev32qs16_1.c: Likewise.
* gcc.target/arm/simd/vrev32qs8_1.c: Likewise.
* gcc.target/arm/simd/vrev32qu16_1.c: Likewise.
* gcc.target/arm/simd/vrev32qu8_1.c: Likewise.
* gcc.target/arm/simd/vrev32s16_1.c: Likewise.
* gcc.target/arm/simd/vrev32s8_1.c: Likewise.
* gcc.target/arm/simd/vrev32u16_1.c: Likewise.
* gcc.target/arm/simd/vrev32u8_1.c: Likewise.
* gcc.target/arm/simd/vrev64f32_1.c: Likewise.
* gcc.target/arm/simd/vrev64p16_1.c: Likewise.
* gcc.target/arm/simd/vrev64p8_1.c: Likewise.
* gcc.target/arm/simd/vrev64qf32_1.c: Likewise.
* gcc.target/arm/simd/vrev64qp16_1.c: Likewise.
* gcc.target/arm/simd/vrev64qp8_1.c: Likewise.
* gcc.target/arm/simd/vrev64qs16_1.c: Likewise.
* gcc.target/arm/simd/vrev64qs32_1.c: Likewise.
* gcc.target/arm/simd/vrev64qs8_1.c: Likewise.
* gcc.target/arm/simd/vrev64qu16_1.c: Likewise.
* gcc.target/arm/simd/vrev64qu32_1.c: Likewise.
* gcc.target/arm/simd/vrev64qu8_1.c: Likewise.
* gcc.target/arm/simd/vrev64s16_1.c: Likewise.
* gcc.target/arm/simd/vrev64s32_1.c: Likewise.
* gcc.target/arm/simd/vrev64s8_1.c: Likewise.
* gcc.target/arm/simd/vrev64u16_1.c: Likewise.
* gcc.target/arm/simd/vrev64u32_1.c: Likewise.
* gcc.target/arm/simd/vrev64u8_1.c: Likewise.
* gcc.target/arm/simd/vtrnf32_1.c: Likewise.
* gcc.target/arm/simd/vtrnp16_1.c: Likewise.
* gcc.target/arm/simd/vtrnp8_1.c: Likewise.
* gcc.target/arm/simd/vtrnqf32_1.c: Likewise.
* gcc.target/arm/simd/vtrnqp16_1.c: Likewise.
* gcc.target/arm/simd/vtrnqp8_1.c: Likewise.
* gcc.target/arm/simd/vtrnqs16_1.c: Likewise.
* gcc.target/arm/simd/vtrnqs32_1.c: Likewise.
* gcc.target/arm/simd/vtrnqs8_1.c: Likewise.
* gcc.target/arm/simd/vtrnqu16_1.c: Likewise.
* gcc.target/arm/simd/vtrnqu32_1.c: Likewise.
* gcc.target/arm/simd/vtrnqu8_1.c: Likewise.
* gcc.target/arm/simd/vtrns16_1.c: Likewise.
* gcc.target/arm/simd/vtrns32_1.c: Likewise.
* gcc.target/arm/simd/vtrns8_1.c: Likewise.
* gcc.target/arm/simd/vtrnu16_1.c: Likewise.
* gcc.target/arm/simd/vtrnu32_1.c: Likewise.
* gcc.target/arm/simd/vtrnu8_1.c: Likewise.
* gcc.target/arm/simd/vuzpf32_1.c: Likewise.
* gcc.target/arm/simd/vuzpp16_1.c: Likewise.
* gcc.target/arm/simd/vuzpp8_1.c: Likewise.
* gcc.target/arm/simd/vuzpqf32_1.c: Likewise.
* gcc.target/arm/simd/vuzpqp16_1.c: Likewise.
* gcc.target/arm/simd/vuzpqp8_1.c: Likewise.
* gcc.target/arm/simd/vuzpqs16_1.c: Likewise.
* gcc.target/arm/simd/vuzpqs32_1.c: Likewise.
* gcc.target/arm/simd/vuzpqs8_1.c: Likewise.
* gcc.target/arm/simd/vuzpqu16_1.c: Likewise.
* gcc.target/arm/simd/vuzpqu32_1.c: Likewise.
* gcc.target/arm/simd/vuzpqu8_1.c: Likewise.
* gcc.target/arm/simd/vuzps16_1.c: Likewise.
* gcc.target/arm/simd/vuzps32_1.c: Likewise.
* gcc.target/arm/simd/vuzps8_1.c: Likewise.
* gcc.target/arm/simd/vuzpu16_1.c: Likewise.
* gcc.target/arm/simd/vuzpu32_1.c: Likewise.
* gcc.target/arm/simd/vuzpu8_1.c: Likewise.
* gcc.target/arm/simd/vzipf32_1.c: Likewise.
* gcc.target/arm/simd/vzipp16_1.c: Likewise.
* gcc.target/arm/simd/vzipp8_1.c: Likewise.
* gcc.target/arm/simd/vzipqf32_1.c: Likewise.
* gcc.target/arm/simd/vzipqp16_1.c: Likewise.
* gcc.target/arm/simd/vzipqp8_1.c: Likewise.
* gcc.target/arm/simd/vzipqs16_1.c: Likewise.
* gcc.target/arm/simd/vzipqs32_1.c: Likewise.
* gcc.target/arm/simd/vzipqs8_1.c: Likewise.
* gcc.target/arm/simd/vzipqu16_1.c: Likewise.
* gcc.target/arm/simd/vzipqu32_1.c: Likewise.
* gcc.target/arm/simd/vzipqu8_1.c: Likewise.
* gcc.target/arm/simd/vzips16_1.c: Likewise.
* gcc.target/arm/simd/vzips32_1.c: Likewise.
* gcc.target/arm/simd/vzips8_1.c: Likewise.
* gcc.target/arm/simd/vzipu16_1.c: Likewise.
* gcc.target/arm/simd/vzipu32_1.c: Likewise.
* gcc.target/arm/simd/vzipu8_1.c: Likewise.
Change-Id: Iff2ac73df9a851db93cae44d799c2457b4d1b0a3
Diffstat (limited to 'gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c index 9a373ec4100..f294c2f277e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_s16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ |