diff options
| author | Andrew Pinski <apinski@marvell.com> | 2022-11-15 04:59:51 +0000 |
|---|---|---|
| committer | Andrew Pinski <apinski@marvell.com> | 2022-11-15 04:59:51 +0000 |
| commit | 73b582a8e34a3c523c8ece0c6674f473acecab53 (patch) | |
| tree | bffe35425d513e1644301d20a56db4aa704ad2cf /gcc/doc/invoke.texi | |
| parent | 7dc52ed58b754da4e2e26e50854af835f07520f4 (diff) | |
Remove Score documentation
Score target support was removed in r5-3909-g3daa7bbf791203
but it looks like some of the documentation was missed.
This removes it.
Committed as obvious after a "make html".
Thanks,
Andrew
gcc/ChangeLog:
* doc/invoke.texi: Remove Score option section.
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 52 |
1 files changed, 0 insertions, 52 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ef88f2a6b3f..55e8a14fecd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1316,13 +1316,6 @@ See RS/6000 and PowerPC Options. -mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard @gol -mhotpatch=@var{halfwords},@var{halfwords}} -@emph{Score Options} -@gccoptlist{-meb -mel @gol --mnhwloop @gol --muls @gol --mmac @gol --mscore5 -mscore5u -mscore7 -mscore7d} - @emph{SH Options} @gccoptlist{-m1 -m2 -m2e @gol -m2a-nofpu -m2a-single-only -m2a-single -m2a @gol @@ -19726,7 +19719,6 @@ platform. * RS/6000 and PowerPC Options:: * RX Options:: * S/390 and zSeries Options:: -* Score Options:: * SH Options:: * Solaris 2 Options:: * SPARC Options:: @@ -30424,50 +30416,6 @@ This option can be overridden for individual functions with the @code{hotpatch} attribute. @end table -@node Score Options -@subsection Score Options -@cindex Score Options - -These options are defined for Score implementations: - -@table @gcctabopt -@item -meb -@opindex meb -Compile code for big-endian mode. This is the default. - -@item -mel -@opindex mel -Compile code for little-endian mode. - -@item -mnhwloop -@opindex mnhwloop -Disable generation of @code{bcnz} instructions. - -@item -muls -@opindex muls -Enable generation of unaligned load and store instructions. - -@item -mmac -@opindex mmac -Enable the use of multiply-accumulate instructions. Disabled by default. - -@item -mscore5 -@opindex mscore5 -Specify the SCORE5 as the target architecture. - -@item -mscore5u -@opindex mscore5u -Specify the SCORE5U of the target architecture. - -@item -mscore7 -@opindex mscore7 -Specify the SCORE7 as the target architecture. This is the default. - -@item -mscore7d -@opindex mscore7d -Specify the SCORE7D as the target architecture. -@end table - @node SH Options @subsection SH Options |