[gcc]

2015-04-23  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	Backport from mainline r222349
	2015-04-22  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/65456
	* config/rs6000/rs6000.c (rs6000_option_override_internal):  For
	VSX + POWER8, enable TARGET_ALLOW_MOVMISALIGN and
	TARGET_EFFICIENT_UNALIGNED_VSX if not selected by command line
	option.
	(rs6000_builtin_mask_for_load): Return 0 for targets with
	efficient unaligned VSX accesses so that the vectorizer will use
	direct unaligned loads.
	(rs6000_builtin_support_vector_misalignment): Always return true
	for targets with efficient unaligned VSX accesses.
	(rs6000_builtin_vectorization_cost): Cost of unaligned loads and
	stores on targets with efficient unaligned VSX accesses is almost
	always the same as the cost of an aligned load or store, so model
	it that way.
	* config/rs6000/rs6000.h (SLOW_UNALIGNED_ACCESS): Return 0 for
	unaligned vectors if we have efficient unaligned VSX accesses.
	* config/rs6000/rs6000.opt (mefficient-unaligned-vector): New
	undocumented option.

[gcc/testsuite]

2015-04-23  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	Backport from mainline r222349
	2015-04-22  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/65456
	* gcc.dg/vect/bb-slp-24.c: Exclude test for POWER8.
	* gcc.dg/vect/bb-slp-25.c: Likewise.
	* gcc.dg/vect/bb-slp-29.c: Likewise.
	* gcc.dg/vect/bb-slp-32.c: Replace vect_no_align with
	vect_no_align && { ! vect_hw_misalign }.
	* gcc.dg/vect/bb-slp-9.c: Likewise.
	* gcc.dg/vect/costmodel/ppc/costmodel-slp-33.c: Exclude test for
	vect_hw_misalign.
	* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Likewise.
	* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust tests to
	account for POWER8, where peeling for alignment is not needed.
	* gcc.dg/vect/costmodel/ppc/costmodel-vect-outer-fir.c: Replace
	vect_no_align with vect_no_align && { ! vect_hw_misalign }.
	* gcc.dg.vect.if-cvt-stores-vect-ifcvt-18.c: Likewise.
	* gcc.dg/vect/no-scevccp-outer-6-global.c: Likewise.
	* gcc.dg/vect/no-scevccp-outer-6.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-43.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-57.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-61.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-depend-1.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise.
	* gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise.
	* gcc.dg/vect/pr16105.c: Likewise.
	* gcc.dg/vect/pr20122.c: Likewise.
	* gcc.dg/vect/pr33804.c: Likewise.
	* gcc.dg/vect/pr33953.c: Likewise.
	* gcc.dg/vect/pr56787.c: Likewise.
	* gcc.dg/vect/pr58508.c: Likewise.
	* gcc.dg/vect/slp-25.c: Likewise.
	* gcc.dg/vect/vect-105-bit-array.c: Likewise.
	* gcc.dg/vect/vect-105.c: Likewise.
	* gcc.dg/vect/vect-27.c: Likewise.
	* gcc.dg/vect/vect-29.c: Likewise.
	* gcc.dg/vect/vect-33.c: Exclude unaligned access test for
	POWER8.
	* gcc.dg/vect/vect-42.c: Replace vect_no_align with vect_no_align
	&& { ! vect_hw_misalign }.
	* gcc.dg/vect/vect-44.c: Likewise.
	* gcc.dg/vect/vect-48.c: Likewise.
	* gcc.dg/vect/vect-50.c: Likewise.
	* gcc.dg/vect/vect-52.c: Likewise.
	* gcc.dg/vect/vect-56.c: Likewise.
	* gcc.dg/vect/vect-60.c: Likewise.
	* gcc.dg/vect/vect-72.c: Likewise.
	* gcc.dg/vect/vect-75-big-array.c: Likewise.
	* gcc.dg/vect/vect-75.c: Likewise.
	* gcc.dg/vect/vect-77-alignchecks.c: Likewise.
	* gcc.dg/vect/vect-77-global.c: Likewise.
	* gcc.dg/vect/vect-78-alignchecks.c: Likewise.
	* gcc.dg/vect/vect-78-global.c: Likewise.
	* gcc.dg/vect/vect-93.c: Likewise.
	* gcc.dg/vect/vect-95.c: Likewise.
	* gcc.dg/vect/vect-96.c: Likewise.
	* gcc.dg/vect/vect-cond-1.c: Likewise.
	* gcc.dg/vect/vect-cond-3.c: Likewise.
	* gcc.dg/vect/vect-cond-4.c: Likewise.
	* gcc.dg/vect/vect-cselim-1.c: Likewise.
	* gcc.dg/vect/vect-multitypes-1.c: Likewise.
	* gcc.dg/vect/vect-multitypes-3.c: Likewise.
	* gcc.dg/vect/vect-multitypes-4.c: Likewise.
	* gcc.dg/vect/vect-multitypes-6.c: Likewise.
	* gcc.dg/vect/vect-nest-cycle-1.c: Likewise.
	* gcc.dg/vect/vect-nest-cycle-2.c: Likewise.
	* gcc.dg/vect/vect-outer-3a-big-array.c: Likewise.
	* gcc.dg/vect/vect-outer-3a.c: Likewise.
	* gcc.dg/vect/vect-outer-5.c: Likewise.
	* gcc.dg/vect/vect-outer-fir-big-array.c: Likewise.
	* gcc.dg/vect/vect-outer-fir-lb-big-array.c: Likewise.
	* gcc.dg/vect/vect-outer-fir-lb.c: Likewise.
	* gcc.dg/vect/vect-outer-fir.c: Likewise.
	* gcc.dg/vect/vect-peel-3.c: Likewise.
	* gcc.dg/vect/vect-peel-4.c: Likewise.
	* gcc.dg/vect/vect-pre-interact.c: Likewise.
	* gcc.target/powerpc/pr65456.c: New test.
	* gcc.target/powerpc/vsx-vectorize-2.c: Exclude test for POWER8.
	* gcc.target/powerpc/vsx-vectorize-4.c: Likewise.
	* gcc.target/powerpc/vsx-vectorize-6.c: Likewise.
	* gcc.target/powerpc/vsx-vectorize-7.c: Likewise.
	* gfortran.dg/vect/vect-2.f90: Replace vect_no_align with
	vect_no_align && { ! vect_hw_misalign }.
	* gfortran.dg/vect/vect-3.f90: Likewise.
	* gfortran.dg/vect/vect-4.f90: Likewise.
	* gfortran.dg/vect/vect-5.f90: Likewise.
	* lib/target-supports.exp (check_effective_target_vect_no_align):
	Return 1 for POWER8.
	(check_effective_target_vect_hw_misalign): Return 1 for POWER8.

	Backport from mainline r222372
	2015-04-23  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a.c: Replace
	vect_no_align with vect_no_align && { ! vect_hw_misalign }.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@222386 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 34 insertions, 2 deletions

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 58ea3d106ae..d0d82367185 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4251,6 +4251,22 @@ rs6000_option_override_internal (bool global_init_p)
 	}
     }
 
+  /* Determine when unaligned vector accesses are permitted, and when
+     they are preferred over masked Altivec loads.  Note that if
+     TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
+     TARGET_EFFICIENT_UNALIGNED_VSX must be as well.  The converse is
+     not true.  */
+  if (TARGET_EFFICIENT_UNALIGNED_VSX == -1) {
+    if (TARGET_VSX && rs6000_cpu == PROCESSOR_POWER8
+	&& TARGET_ALLOW_MOVMISALIGN != 0)
+      TARGET_EFFICIENT_UNALIGNED_VSX = 1;
+    else
+      TARGET_EFFICIENT_UNALIGNED_VSX = 0;
+  }
+
+  if (TARGET_ALLOW_MOVMISALIGN == -1 && rs6000_cpu == PROCESSOR_POWER8)
+    TARGET_ALLOW_MOVMISALIGN = 1;
+
   /* Set the builtin mask of the various options used that could affect which
      builtins were used.  In the past we used target_flags, but we've run out
      of bits, and some options like SPE and PAIRED are no longer in
@@ -4299,7 +4315,9 @@ rs6000_option_override (void)
 static tree
 rs6000_builtin_mask_for_load (void)
 {
-  if (TARGET_ALTIVEC || TARGET_VSX)
+  /* Don't use lvsl/vperm for P8 and similarly efficient machines.  */
+  if ((TARGET_ALTIVEC && !TARGET_VSX)
+      || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
     return altivec_builtin_mask_for_load;
   else
     return 0;
@@ -4378,6 +4396,9 @@ rs6000_builtin_support_vector_misalignment (machine_mode mode,
 {
   if (TARGET_VSX)
     {
+      if (TARGET_EFFICIENT_UNALIGNED_VSX)
+	return true;
+
       /* Return if movmisalign pattern is not supported for this mode.  */
       if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
         return false;
@@ -4441,6 +4462,9 @@ rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
         return 3;
 
       case unaligned_load:
+	if (TARGET_EFFICIENT_UNALIGNED_VSX)
+	  return 1;
+
         if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
           {
             elements = TYPE_VECTOR_SUBPARTS (vectype);
@@ -4476,6 +4500,9 @@ rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
         return 2;
 
       case unaligned_store:
+	if (TARGET_EFFICIENT_UNALIGNED_VSX)
+	  return 1;
+
         if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
           {
             elements = TYPE_VECTOR_SUBPARTS (vectype);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ef6bb2f7a53..b13df1b2b6e 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -891,7 +891,8 @@ enum data_align { align_abi, align_opt, align_both };
    || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode	\
 	|| (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)	\
        && (ALIGN) < 32)							\
-   || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
+   || (!TARGET_EFFICIENT_UNALIGNED_VSX                                  \
+       && (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))))
 
 
 /* Standard register usage.  */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index e69910f6567..5bb2718a88f 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -211,6 +211,10 @@ mallow-movmisalign
 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
 ; Allow/disallow the movmisalign in DF/DI vectors
 
+mefficient-unaligned-vector
+Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1)
+; Consider unaligned VSX accesses to be efficient/inefficient
+
 mallow-df-permute
 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
 ; Allow/disallow permutation of DF/DI vectors