diff options
| author | yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-03-05 14:22:20 +0000 |
|---|---|---|
| committer | yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-03-05 14:22:20 +0000 |
| commit | 1d1384dd7748a6c2f6eaf36d348eaa5194ed08f2 (patch) | |
| tree | ad77c701a91195d3dcbeb417f354f26c453c9121 /gcc/config/aarch64 | |
| parent | 6d1f38bb98cf5f8455e35a68393c6f645edf4c29 (diff) | |
gcc/
2015-03-05 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r220860.
2015-02-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_<mode>3):
Mark operand 0 as earlyclobber in 2nd alternative.
(1st define_split below *aarch64_lshr_sisd_or_int_<mode>3):
Write negated shift amount into QI lowpart operand 0 and use it
in the shift step.
(2nd define_split below *aarch64_lshr_sisd_or_int_<mode>3): Likewise.
gcc/testsuite/
2015-03-05 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r220860.
2015-02-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/sisd-shft-neg_1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@221215 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 7b8ec347df0..9e3f6a35d51 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3015,7 +3015,7 @@ ;; Logical right shift using SISD or Integer instruction (define_insn "*aarch64_lshr_sisd_or_int_<mode>3" - [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + [(set (match_operand:GPI 0 "register_operand" "=w,&w,r") (lshiftrt:GPI (match_operand:GPI 1 "register_operand" "w,w,r") (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))] @@ -3034,11 +3034,13 @@ (match_operand:DI 1 "aarch64_simd_register") (match_operand:QI 2 "aarch64_simd_register")))] "TARGET_SIMD && reload_completed" - [(set (match_dup 2) + [(set (match_dup 3) (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) (set (match_dup 0) - (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SISD_USHL))] - "" + (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_SISD_USHL))] + { + operands[3] = gen_lowpart (QImode, operands[0]); + } ) (define_split @@ -3047,11 +3049,13 @@ (match_operand:SI 1 "aarch64_simd_register") (match_operand:QI 2 "aarch64_simd_register")))] "TARGET_SIMD && reload_completed" - [(set (match_dup 2) + [(set (match_dup 3) (unspec:QI [(match_dup 2)] UNSPEC_SISD_NEG)) (set (match_dup 0) - (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_USHL_2S))] - "" + (unspec:SI [(match_dup 1) (match_dup 3)] UNSPEC_USHL_2S))] + { + operands[3] = gen_lowpart (QImode, operands[0]); + } ) ;; Arithmetic right shift using SISD or Integer instruction |