diff options
author | No Author <no-author@gcc.gnu.org> | 2005-04-21 05:20:58 +0000 |
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committer | No Author <no-author@gcc.gnu.org> | 2005-04-21 05:20:58 +0000 |
commit | d89dab3130e93bf415da3719355e24ef4cd039ca (patch) | |
tree | bfc8d23a253a399cac513773505c9a99e0dd70b3 | |
parent | 04e3374e55e78d822da677499f5d9a4388f658e5 (diff) |
This commit was manufactured by cvs2svn to create tagreleases/gcc-4.0.0
'gcc_4_0_0_release'.
From-SVN: r98492
51 files changed, 0 insertions, 4373 deletions
diff --git a/gcc/config/bfin/bfin-modes.def b/gcc/config/bfin/bfin-modes.def deleted file mode 100644 index 18ed3156941..00000000000 --- a/gcc/config/bfin/bfin-modes.def +++ /dev/null @@ -1,25 +0,0 @@ -/* Definitions of target machine for GNU compiler, for Blackfin. - Copyright (C) 2005 Free Software Foundation, Inc. - Contributed by Analog Devices. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, - MA 02111-1307, USA. */ - -/* PDImode for the 40 bit accumulators. */ -PARTIAL_INT_MODE (DI); - -VECTOR_MODE (INT, HI, 2); /* V2HI */ diff --git a/gcc/config/bfin/bfin-protos.h b/gcc/config/bfin/bfin-protos.h deleted file mode 100644 index e75046aeb19..00000000000 --- a/gcc/config/bfin/bfin-protos.h +++ /dev/null @@ -1,88 +0,0 @@ -/* Prototypes for Blackfin functions used in the md file & elsewhere. - Copyright (C) 2005 Free Software Foundation, Inc. - - This file is part of GNU CC. - - GNU CC is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GNU CC is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GNU CC; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ - -/* Function prototypes that cannot exist in bfin.h due to dependency - complications. */ -#ifndef GCC_BFIN_PROTOS_H -#define GCC_BFIN_PROTOS_H - -#define Mmode enum machine_mode - -extern rtx function_arg (CUMULATIVE_ARGS *, Mmode, tree, int); -extern void function_arg_advance (CUMULATIVE_ARGS *, Mmode, tree, int); -extern bool function_arg_regno_p (int); - -extern const char *output_load_immediate (rtx *); -extern const char *output_casesi_internal (rtx *); -extern char *bfin_asm_long (void); -extern char *bfin_asm_short (void); -extern int log2constp (unsigned HOST_WIDE_INT); - -extern rtx legitimize_address (rtx, rtx, Mmode); -extern int hard_regno_mode_ok (int, Mmode); -extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx); -extern int bfin_frame_pointer_required (void); -extern HOST_WIDE_INT bfin_initial_elimination_offset (int, int); - -extern int effective_address_32bit_p (rtx, Mmode); -extern int symbolic_reference_mentioned_p (rtx); -extern rtx bfin_gen_compare (rtx, Mmode); -extern void expand_move (rtx *, Mmode); -extern void bfin_expand_call (rtx, rtx, rtx, int); -extern bool bfin_expand_strmov (rtx, rtx, rtx, rtx); - -extern void conditional_register_usage (void); -extern int bfin_register_move_cost (enum machine_mode, enum reg_class, - enum reg_class); -extern int bfin_memory_move_cost (enum machine_mode, enum reg_class, int in); -extern enum reg_class secondary_input_reload_class (enum reg_class, Mmode, - rtx); -extern enum reg_class secondary_output_reload_class (enum reg_class, Mmode, - rtx); -extern char *section_asm_op_1 (SECT_ENUM_T); -extern char *section_asm_op (SECT_ENUM_T); -extern void override_options (void); -extern void print_operand (FILE *, rtx, char); -extern void print_address_operand (FILE *, rtx); -extern void split_di (rtx [], int, rtx [], rtx []); -extern int split_load_immediate (rtx []); -extern rtx legitimize_pic_address (rtx, rtx); -extern void emit_pic_move (rtx *, Mmode); -extern void override_options (void); -extern void asm_conditional_branch (rtx, rtx *, int, int); -extern rtx bfin_gen_compare (rtx, Mmode); - -extern int bfin_return_in_memory (tree); -extern void initialize_trampoline (rtx, rtx, rtx); -extern bool bfin_legitimate_address_p (Mmode, rtx, int); -extern rtx bfin_va_arg (tree, tree); - -extern void bfin_expand_prologue (void); -extern void bfin_expand_epilogue (int, int); -extern int push_multiple_operation (rtx, Mmode); -extern int pop_multiple_operation (rtx, Mmode); -extern void output_push_multiple (rtx, rtx *); -extern void output_pop_multiple (rtx, rtx *); -extern int bfin_hard_regno_rename_ok (unsigned int, unsigned int); -extern rtx bfin_return_addr_rtx (int); -#undef Mmode - -#endif - diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h deleted file mode 100644 index 512525afb81..00000000000 --- a/gcc/config/bfin/bfin.h +++ /dev/null @@ -1,1154 +0,0 @@ -/* Definitions for the Blackfin port. - Copyright (C) 2005 Free Software Foundation, Inc. - Contributed by Analog Devices. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ - -#ifndef _BFIN_CONFIG -#define _BFIN_CONFIG - -#define OBJECT_FORMAT_ELF - -#define BRT 1 -#define BRF 0 - -/* Print subsidiary information on the compiler version in use. */ -#define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") - -/* Run-time compilation parameters selecting different hardware subsets. */ - -extern int target_flags; - -/* Predefinition in the preprocessor for this target machine */ -#ifndef TARGET_CPU_CPP_BUILTINS -#define TARGET_CPU_CPP_BUILTINS() \ - do \ - { \ - builtin_define ("bfin"); \ - builtin_define ("BFIN"); \ - } \ - while (0) -#endif - -/* Generate DSP instructions, like DSP halfword loads */ -#define TARGET_DSP (1) - -#define TARGET_DEFAULT MASK_CSYNC - -/* Maximum number of library ids we permit */ -#define MAX_LIBRARY_ID 255 - -extern const char *bfin_library_id_string; - -/* Sometimes certain combinations of command options do not make - sense on a particular target machine. You can define a macro - `OVERRIDE_OPTIONS' to take account of this. This macro, if - defined, is executed once just after all the command options have - been parsed. - - Don't use this macro to turn on various extra optimizations for - `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ - -#define OVERRIDE_OPTIONS override_options () - -#define FUNCTION_MODE SImode -#define Pmode SImode - -/* store-condition-codes instructions store 0 for false - This is the value stored for true. */ -#define STORE_FLAG_VALUE 1 - -/* Define this if pushing a word on the stack - makes the stack pointer a smaller address. */ -#define STACK_GROWS_DOWNWARD - -#define STACK_PUSH_CODE PRE_DEC - -/* Define this if the nominal address of the stack frame - is at the high-address end of the local variables; - that is, each additional local variable allocated - goes at a more negative offset in the frame. */ -#define FRAME_GROWS_DOWNWARD - -/* We define a dummy ARGP register; the parameters start at offset 0 from - it. */ -#define FIRST_PARM_OFFSET(DECL) 0 - -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. */ -#define STARTING_FRAME_OFFSET 0 - -/* Register to use for pushing function arguments. */ -#define STACK_POINTER_REGNUM REG_P6 - -/* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM REG_P7 - -/* A dummy register that will be eliminated to either FP or SP. */ -#define ARG_POINTER_REGNUM REG_ARGP - -/* `PIC_OFFSET_TABLE_REGNUM' - The register number of the register used to address a table of - static data addresses in memory. In some cases this register is - defined by a processor's "application binary interface" (ABI). - When this macro is defined, RTL is generated for this register - once, as with the stack pointer and frame pointer registers. If - this macro is not defined, it is up to the machine-dependent files - to allocate such a register (if necessary). */ -#define PIC_OFFSET_TABLE_REGNUM (REG_P5) - -/* A static chain register for nested functions. We need to use a - call-clobbered register for this. */ -#define STATIC_CHAIN_REGNUM REG_P2 - -/* Define this if functions should assume that stack space has been - allocated for arguments even when their values are passed in - registers. - - The value of this macro is the size, in bytes, of the area reserved for - arguments passed in registers. - - This space can either be allocated by the caller or be a part of the - machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' - says which. */ -#define FIXED_STACK_AREA 12 -#define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA - -/* Define this if the above stack space is to be considered part of the - * space allocated by the caller. */ -#define OUTGOING_REG_PARM_STACK_SPACE - -/* Define this if the maximum size of all the outgoing args is to be - accumulated and pushed during the prologue. The amount can be - found in the variable current_function_outgoing_args_size. */ -#define ACCUMULATE_OUTGOING_ARGS 1 - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. -*/ -#define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ()) - -#define PARM_BOUNDRY 32 - -#define STACK_BOUNDRY 32 - -/*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ - -/* Make strings word-aligned so strcpy from constants will be faster. */ -#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ - (TREE_CODE (EXP) == STRING_CST \ - && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) - -#define TRAMPOLINE_SIZE 18 -#define TRAMPOLINE_TEMPLATE(FILE) \ - fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \ - fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */; \ - fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */; \ - fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */; \ - fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ - -#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ - initialize_trampoline (TRAMP, FNADDR, CXT) - -/* Definitions for register eliminations. - - This is an array of structures. Each structure initializes one pair - of eliminable registers. The "from" register number is given first, - followed by "to". Eliminations of the same "from" register are listed - in order of preference. - - There are two registers that can always be eliminated on the i386. - The frame pointer and the arg pointer can be replaced by either the - hard frame pointer or to the stack pointer, depending upon the - circumstances. The hard frame pointer is not used before reload and - so it is not eligible for elimination. */ - -#define ELIMINABLE_REGS \ -{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ - { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ - -/* Given FROM and TO register numbers, say whether this elimination is - allowed. Frame pointer elimination is automatically handled. - - All other eliminations are valid. */ - -#define CAN_ELIMINATE(FROM, TO) \ - ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) - -/* Define the offset between two registers, one to be eliminated, and the other - its replacement, at the start of a routine. */ - -#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ - ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) - -/* This processor has - 8 data register for doing arithmetic - 8 pointer register for doing addressing, including - 1 stack pointer P6 - 1 frame pointer P7 - 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) - 1 condition code flag register CC - 5 return address registers RETS/I/X/N/E - 1 arithmetic status register (ASTAT). */ - -#define FIRST_PSEUDO_REGISTER 44 - -#define PREG_P(X) (REG_P (X) && REGNO (X) >= REG_P0 && REGNO (X) <= REG_P7) -#define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) -#define D_REGNO_P(X) ((X) <= REG_R7) - -#define REGISTER_NAMES { \ - "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ - "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ - "I0", "B0", "L0", "I1", "B1", "L1", "I2", "B2", \ - "L2", "I3", "B3", "L3", "M0", "M1", "M2", "M3", \ - "A0", "A1", \ - "CC", \ - "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ - "ARGP" \ -} - -#define SHORT_REGISTER_NAMES { \ - "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ - "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ - "I0.L", "B0.L", "L0.L", "I1.L", "B1.L", "L1.L", "I2.L", "B2.L", \ - "L2.L", "I3.L", "B3.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } - -#define HIGH_REGISTER_NAMES { \ - "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ - "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ - "I0.H", "B0.H", "L0.H", "I1.H", "B1.H", "L1.H", "I2.H", "B2.H", \ - "L2.H", "I3.H", "B3.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } - -#define DREGS_PAIR_NAMES { \ - "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } - -#define BYTE_REGISTER_NAMES { \ - "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } - - -/* 1 for registers that have pervasive standard uses - and are not available for the register allocator. */ - -#define FIXED_REGISTERS \ -/*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ -{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ -/*i0 b0 l0 i1 b1 l1 i2 b2 l2 i3 b3 l3 m0 m1 m2 m3 */ \ - 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \ -/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \ - 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ -} - -/* 1 for registers not available across function calls. - These must include the FIXED_REGISTERS and also any - registers that can be used without being saved. - The latter must include the registers where values are returned - and the register where structure-value addresses are passed. - Aside from that, you can include as many other registers as you like. */ - -#define CALL_USED_REGISTERS \ -/*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ -{ 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ -/*i0 b0 l0 i1 b1 l1 i2 b2 l2 i3 b3 l3 m0 m1 m2 m3 */ \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -/*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ -} - -/* Order in which to allocate registers. Each register must be - listed once, even those in FIXED_REGISTERS. List frame pointer - late and fixed registers last. Note that, in general, we prefer - registers listed in CALL_USED_REGISTERS, keeping the others - available for storage of persistent values. */ - -#define REG_ALLOC_ORDER \ -{ REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ - REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ - REG_A0, REG_A1, \ - REG_I0, REG_B0, REG_L0, REG_I1, REG_B1, REG_L1, REG_I2, REG_B2, \ - REG_L2, REG_I3, REG_B3, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ - REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ - REG_ASTAT, REG_SEQSTAT, REG_USP, \ - REG_CC, REG_ARGP \ -} - -/* Macro to conditionally modify fixed_regs/call_used_regs. */ -#define CONDITIONAL_REGISTER_USAGE \ - { \ - conditional_register_usage(); \ - if (flag_pic) \ - { \ - fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - } \ - } - -/* Define the classes of registers for register constraints in the - machine description. Also define ranges of constants. - - One of the classes must always be named ALL_REGS and include all hard regs. - If there is more than one class, another class must be named NO_REGS - and contain no registers. - - The name GENERAL_REGS must be the name of a class (or an alias for - another name such as ALL_REGS). This is the class of registers - that is allowed by "g" or "r" in a register constraint. - Also, registers outside this class are allocated only when - instructions express preferences for them. - - The classes must be numbered in nondecreasing order; that is, - a larger-numbered class must never be contained completely - in a smaller-numbered class. - - For any two classes, it is very desirable that there be another - class that represents their union. */ - - -enum reg_class -{ - NO_REGS, - IREGS, - BREGS, - LREGS, - MREGS, - CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ - DAGREGS, - EVEN_AREGS, - ODD_AREGS, - AREGS, - CCREGS, - EVEN_DREGS, - ODD_DREGS, - DREGS, - PREGS_CLOBBERED, - PREGS, - DPREGS, - MOST_REGS, - PROLOGUE_REGS, - NON_A_CC_REGS, - ALL_REGS, LIM_REG_CLASSES -}; - -#define N_REG_CLASSES ((int)LIM_REG_CLASSES) - -#define GENERAL_REGS DPREGS - -/* Give names of register classes as strings for dump file. */ - -#define REG_CLASS_NAMES \ -{ "NO_REGS", \ - "IREGS", \ - "BREGS", \ - "LREGS", \ - "MREGS", \ - "CIRCREGS", \ - "DAGREGS", \ - "EVEN_AREGS", \ - "ODD_AREGS", \ - "AREGS", \ - "CCREGS", \ - "EVEN_DREGS", \ - "ODD_DREGS", \ - "DREGS", \ - "PREGS_CLOBBERED", \ - "PREGS", \ - "DPREGS", \ - "MOST_REGS", \ - "PROLOGUE_REGS", \ - "NON_A_CC_REGS", \ - "ALL_REGS" } - -/* An initializer containing the contents of the register classes, as integers - which are bit masks. The Nth integer specifies the contents of class N. - The way the integer MASK is interpreted is that register R is in the class - if `MASK & (1 << R)' is 1. - - When the machine has more than 32 registers, an integer does not suffice. - Then the integers are replaced by sub-initializers, braced groupings - containing several integers. Each sub-initializer must be suitable as an - initializer for the type `HARD_REG_SET' which is defined in - `hard-reg-set.h'. */ - -/* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use - MOST_REGS as the union of DPREGS and DAGREGS. */ - -#define REG_CLASS_CONTENTS \ - /* 31 - 0 63-32 */ \ -{ { 0x00000000, 0 }, /* NO_REGS */ \ - { 0x02490000, 0 }, /* IREGS */ \ - { 0x04920000, 0 }, /* BREGS */ \ - { 0x09240000, 0 }, /* LREGS */ \ - { 0xf0000000, 0 }, /* MREGS */ \ - { 0x0fff0000, 0 }, /* CIRCREGS */ \ - { 0xffff0000, 0 }, /* DAGREGS */ \ - { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ - { 0x00000000, 0x2 }, /* ODD_AREGS */ \ - { 0x00000000, 0x3 }, /* AREGS */ \ - { 0x00000000, 0x4 }, /* CCREGS */ \ - { 0x00000055, 0 }, /* EVEN_DREGS */ \ - { 0x000000aa, 0 }, /* ODD_DREGS */ \ - { 0x000000ff, 0 }, /* DREGS */ \ - { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ - { 0x0000ff00, 0x800 }, /* PREGS */ \ - { 0x0000ffff, 0x800 }, /* DPREGS */ \ - { 0xffffffff, 0x800 }, /* MOST_REGS */\ - { 0x00000000, 0x7f8 }, /* PROLOGUE_REGS */\ - { 0xffffffff, 0xff8 }, /* NON_A_CC_REGS */\ - { 0xffffffff, 0xfff }} /* ALL_REGS */ - -#define BASE_REG_CLASS PREGS -#define INDEX_REG_CLASS PREGS - -#define REGNO_OK_FOR_BASE_STRICT_P(X) (REGNO_REG_CLASS (X) == BASE_REG_CLASS) -#define REGNO_OK_FOR_BASE_NONSTRICT_P(X) \ - (((X) >= FIRST_PSEUDO_REGISTER) || REGNO_REG_CLASS (X) == BASE_REG_CLASS) - -#ifdef REG_OK_STRICT -#define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X) -#else -#define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X) -#endif - -#define REG_OK_FOR_BASE_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) -#define REG_OK_FOR_INDEX_P(X) 0 -#define REGNO_OK_FOR_INDEX_P(X) 0 - -/* Get reg_class from a letter such as appears in the machine description. */ - -#define REG_CLASS_FROM_LETTER(LETTER) \ - ((LETTER) == 'a' ? PREGS : \ - (LETTER) == 'd' ? DREGS : \ - (LETTER) == 'z' ? PREGS_CLOBBERED : \ - (LETTER) == 'D' ? EVEN_DREGS : \ - (LETTER) == 'W' ? ODD_DREGS : \ - (LETTER) == 'e' ? AREGS : \ - (LETTER) == 'A' ? EVEN_AREGS : \ - (LETTER) == 'B' ? ODD_AREGS : \ - (LETTER) == 'b' ? IREGS : \ - (LETTER) == 'B' ? BREGS : \ - (LETTER) == 'f' ? MREGS : \ - (LETTER) == 'c' ? CIRCREGS : \ - (LETTER) == 'C' ? CCREGS : \ - (LETTER) == 'x' ? MOST_REGS : \ - (LETTER) == 'y' ? PROLOGUE_REGS : \ - (LETTER) == 'w' ? NON_A_CC_REGS : \ - NO_REGS) - -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ - -#define REGNO_REG_CLASS(REGNO) \ - ((REGNO) < REG_P0 ? DREGS \ - : (REGNO) < REG_I0 ? PREGS \ - : (REGNO) == REG_ARGP ? BASE_REG_CLASS \ - : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ - : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ - : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ - : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ - : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ - : (REGNO) == REG_CC ? CCREGS \ - : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ - : NO_REGS) - -/* When defined, the compiler allows registers explicitly used in the - rtl to be used as spill registers but prevents the compiler from - extending the lifetime of these registers. */ -#define SMALL_REGISTER_CLASSES 1 - -#define CLASS_LIKELY_SPILLED_P(CLASS) \ - ((CLASS) == PREGS_CLOBBERED \ - || (CLASS) == PROLOGUE_REGS \ - || (CLASS) == CCREGS) - -/* Do not allow to store a value in REG_CC for any mode */ -/* Do not allow to store value in pregs if mode is not SI*/ -#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) - -/* Return the maximum number of consecutive registers - needed to represent mode MODE in a register of class CLASS. */ -#define CLASS_MAX_NREGS(CLASS, MODE) \ - ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) - -#define HARD_REGNO_NREGS(REGNO, MODE) \ -((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) \ - ? 1 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) - -/* A C expression that is nonzero if hard register TO can be - considered for use as a rename register for FROM register */ -#define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) - -/* A C expression that is nonzero if it is desirable to choose - register allocation so as to avoid move instructions between a - value of mode MODE1 and a value of mode MODE2. - - If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, - MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, - MODE2)' must be zero. */ -#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) - -/* `PREFERRED_RELOAD_CLASS (X, CLASS)' - A C expression that places additional restrictions on the register - class to use when it is necessary to copy value X into a register - in class CLASS. The value is a register class; perhaps CLASS, or - perhaps another, smaller class. */ -#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) - -#define SECONDARY_OUTPUT_RELOAD_CLASS(class,mode,x) \ - secondary_output_reload_class(class,mode,x) -#define SECONDARY_INPUT_RELOAD_CLASS(class,mode,x) \ - secondary_input_reload_class(class,mode,x) - -/* Function Calling Conventions. */ - -/* The type of the current function; normal functions are of type - SUBROUTINE. */ -typedef enum { - SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER -} e_funkind; - -#define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } - -typedef struct { - int words; /* # words passed so far */ - int nregs; /* # registers available for passing */ - int *arg_regs; /* array of register -1 terminated */ -} CUMULATIVE_ARGS; - -/* Define where to put the arguments to a function. - Value is zero to push the argument on the stack, - or a hard register in which to store the argument. - - MODE is the argument's machine mode. - TYPE is the data type of the argument (as a tree). - This is null for libcalls where that information may - not be available. - CUM is a variable of type CUMULATIVE_ARGS which gives info about - the preceding args and about the function being called. - NAMED is nonzero if this argument is a named parameter - (otherwise it is an extra parameter matching an ellipsis). */ - -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ - (function_arg (&CUM, MODE, TYPE, NAMED)) - -#define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) - - -/* Initialize a variable CUM of type CUMULATIVE_ARGS - for a call to a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. */ -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ - (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) - -/* Update the data in CUM to advance over an argument - of mode MODE and data type TYPE. - (TYPE is null for libcalls where that information may not be available.) */ -#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - (function_arg_advance (&CUM, MODE, TYPE, NAMED)) - -#define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0 - -/* Define how to find the value returned by a function. - VALTYPE is the data type of the value (as a tree). - If the precise function being called is known, FUNC is its FUNCTION_DECL; - otherwise, FUNC is 0. -*/ - -#define VALUE_REGNO(MODE) (REG_R0) - -#define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx_REG (TYPE_MODE (VALTYPE), \ - VALUE_REGNO(TYPE_MODE(VALTYPE))) - -/* Define how to find the value returned by a library function - assuming the value has mode MODE. */ - -#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) - -#define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) - -#define DEFAULT_PCC_STRUCT_RETURN 0 -#define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE) - -/* Before the prologue, the return address is in the RETS register. */ -#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) - -#define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) - -#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) - -/* Call instructions don't modify the stack pointer on the Blackfin. */ -#define INCOMING_FRAME_SP_OFFSET 0 - -/* Describe how we implement __builtin_eh_return. */ -#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) -#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) -#define EH_RETURN_HANDLER_RTX \ - gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) - -/* Addressing Modes */ - -/* Recognize any constant value that is a valid address. */ -#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) - -/* Nonzero if the constant value X is a legitimate general operand. - symbol_ref are not legitimate and will be put into constant pool. - See force_const_mem(). - If -mno-pool, all constants are legitimate. - */ -#define LEGITIMATE_CONSTANT_P(x) 1 - -/* A number, the maximum number of registers that can appear in a - valid memory address. Note that it is up to you to specify a - value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS' - would ever accept. */ -#define MAX_REGS_PER_ADDRESS 1 - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - Blackfin addressing modes are as follows: - - [preg] - [preg + imm16] - - B [ Preg + uimm15 ] - W [ Preg + uimm16m2 ] - [ Preg + uimm17m4 ] - - [preg++] - [preg--] - [--sp] -*/ - -#define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ - (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) - -#ifdef REG_OK_STRICT -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ - do { \ - if (bfin_legitimate_address_p (MODE, X, 1)) \ - goto WIN; \ - } while (0); -#else -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ - do { \ - if (bfin_legitimate_address_p (MODE, X, 0)) \ - goto WIN; \ - } while (0); -#endif - -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. - */ -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ -do { \ - rtx _q = legitimize_address(X, OLDX, MODE); \ - if (_q) { X = _q; goto WIN; } \ -} while (0) - -#define HAVE_POST_INCREMENT 1 -#define HAVE_POST_DECREMENT 1 -#define HAVE_PRE_DECREMENT 1 - -/* `LEGITIMATE_PIC_OPERAND_P (X)' - A C expression that is nonzero if X is a legitimate immediate - operand on the target machine when generating position independent - code. You can assume that X satisfies `CONSTANT_P', so you need - not check this. You can also assume FLAG_PIC is true, so you need - not check it either. You need not define this macro if all - constants (including `SYMBOL_REF') can be immediate operands when - generating position independent code. */ -#define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) - -#define SYMBOLIC_CONST(X) \ -(GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == LABEL_REF \ - || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) - -/* - A C statement or compound statement with a conditional `goto - LABEL;' executed if memory address X (an RTX) can have different - meanings depending on the machine mode of the memory reference it - is used for or if the address is valid for some modes but not - others. - - Autoincrement and autodecrement addresses typically have - mode-dependent effects because the amount of the increment or - decrement is the size of the operand being addressed. Some - machines have other mode-dependent addresses. Many RISC machines - have no mode-dependent addresses. - - You may assume that ADDR is a valid address for the machine. -*/ -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ -do { \ - if (GET_CODE (ADDR) == POST_INC \ - || GET_CODE (ADDR) == POST_DEC \ - || GET_CODE (ADDR) == PRE_DEC) \ - goto LABEL; \ -} while (0) - -#define NOTICE_UPDATE_CC(EXPR, INSN) 0 - -/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits - is done just by pretending it is already truncated. */ -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 - -/* Max number of bytes we can move from memory to memory - in one reasonably fast instruction. */ -#define MOVE_MAX UNITS_PER_WORD - - -/* STORAGE LAYOUT: target machine storage layout - Define this macro as a C expression which is nonzero if accessing - less than a word of memory (i.e. a `char' or a `short') is no - faster than accessing a word of memory, i.e., if such access - require more than one instruction or if there is no difference in - cost between byte and (aligned) word loads. - - When this macro is not defined, the compiler will access a field by - finding the smallest containing object; when it is defined, a - fullword load will be used if alignment permits. Unless bytes - accesses are faster than word accesses, using word accesses is - preferable since it may eliminate subsequent memory access if - subsequent accesses occur to other fields in the same word of the - structure, but to different bytes. */ -#define SLOW_BYTE_ACCESS 0 -#define SLOW_SHORT_ACCESS 0 - -/* Define this if most significant bit is lowest numbered - in instructions that operate on numbered bit-fields. */ -#define BITS_BIG_ENDIAN 0 - -/* Define this if most significant byte of a word is the lowest numbered. - We can't access bytes but if we could we would in the Big Endian order. */ -#define BYTES_BIG_ENDIAN 0 - -/* Define this if most significant word of a multiword number is numbered. */ -#define WORDS_BIG_ENDIAN 0 - -/* number of bits in an addressable storage unit */ -#define BITS_PER_UNIT 8 - -/* Width in bits of a "word", which is the contents of a machine register. - Note that this is not necessarily the width of data type `int'; - if using 16-bit ints on a 68000, this would still be 32. - But on a machine with 16-bit registers, this would be 16. */ -#define BITS_PER_WORD 32 - -/* Width of a word, in units (bytes). */ -#define UNITS_PER_WORD 4 - -/* Size of a vector for autovectorization. */ -#define UNITS_PER_SIMD_WORD 4 - -/* Width in bits of a pointer. - See also the macro `Pmode1' defined below. */ -#define POINTER_SIZE 32 - -/* Allocation boundary (in *bits*) for storing pointers in memory. */ -#define POINTER_BOUNDARY 32 - -/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY 32 - -/* Boundary (in *bits*) on which stack pointer should be aligned. */ -#define STACK_BOUNDARY 32 - -/* Allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY 32 - -/* Alignment of field after `int : 0' in a structure. */ -#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD - -/* No data type wants to be aligned rounder than this. */ -#define BIGGEST_ALIGNMENT 32 - -/* Define this if move instructions will actually fail to work - when given unaligned data. */ -#define STRICT_ALIGNMENT 1 - -/* (shell-command "rm c-decl.o stor-layout.o") - * never define PCC_BITFIELD_TYPE_MATTERS - * really cause some alignment problem - */ - -#define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ - BITS_PER_UNIT) - -#define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ - BITS_PER_UNIT) - - -/* what is the 'type' of size_t */ -#define SIZE_TYPE "long unsigned int" - -/* Define this as 1 if `char' should by default be signed; else as 0. */ -#define DEFAULT_SIGNED_CHAR 1 -#define FLOAT_TYPE_SIZE BITS_PER_WORD -#define SHORT_TYPE_SIZE 16 -#define CHAR_TYPE_SIZE 8 -#define INT_TYPE_SIZE 32 -#define LONG_TYPE_SIZE 32 -#define LONG_LONG_TYPE_SIZE 64 - -/* Note: Fix this to depend on target switch. -- lev */ - -/* Note: Try to implement double and force long double. -- tonyko - * #define __DOUBLES_ARE_FLOATS__ - * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE - * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE - * #define DOUBLES_ARE_FLOATS 1 - */ - -#define DOUBLE_TYPE_SIZE 64 -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' - A macro to update M and UNSIGNEDP when an object whose type is - TYPE and which has the specified mode and signedness is to be - stored in a register. This macro is only called when TYPE is a - scalar type. - - On most RISC machines, which only have operations that operate on - a full register, define this macro to set M to `word_mode' if M is - an integer mode narrower than `BITS_PER_WORD'. In most cases, - only integer modes should be widened because wider-precision - floating-point operations are usually more expensive than their - narrower counterparts. - - For most machines, the macro definition does not change UNSIGNEDP. - However, some machines, have instructions that preferentially - handle either signed or unsigned quantities of certain modes. For - example, on the DEC Alpha, 32-bit loads from memory and 32-bit add - instructions sign-extend the result to 64 bits. On such machines, - set UNSIGNEDP according to which kind of extension is more - efficient. - - Do not define this macro if it would never modify M.*/ - -#define BFIN_PROMOTE_MODE_P(MODE) \ - (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ - && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) - -#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ - if (BFIN_PROMOTE_MODE_P(MODE)) \ - { \ - if (MODE == QImode) \ - UNSIGNEDP = 1; \ - else if (MODE == HImode) \ - UNSIGNEDP = 0; \ - (MODE) = SImode; \ - } - -/* Describing Relative Costs of Operations */ - -/* Do not put function addr into constant pool */ -#define NO_FUNCTION_CSE 1 - -/* A C expression for the cost of moving data from a register in class FROM to - one in class TO. The classes are expressed using the enumeration values - such as `GENERAL_REGS'. A value of 2 is the default; other values are - interpreted relative to that. - - It is not required that the cost always equal 2 when FROM is the same as TO; - on some machines it is expensive to move between registers if they are not - general registers. */ - -#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ - bfin_register_move_cost ((MODE), (CLASS1), (CLASS2)) - -/* A C expression for the cost of moving data of mode M between a - register and memory. A value of 2 is the default; this cost is - relative to those in `REGISTER_MOVE_COST'. - - If moving between registers and memory is more expensive than - between two registers, you should define this macro to express the - relative cost. */ - -#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ - bfin_memory_move_cost ((MODE), (CLASS), (IN)) - -/* Specify the machine mode that this machine uses - for the index in the tablejump instruction. */ -#define CASE_VECTOR_MODE SImode - -#define JUMP_TABLES_IN_TEXT_SECTION flag_pic - -/* Define if operations between registers always perform the operation - on the full register even if a narrower mode is specified. -#define WORD_REGISTER_OPERATIONS -*/ - -#define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140) -#define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767) -#define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535) -#define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63) -#define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0) -#define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31) -#define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7) -#define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15) -#define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3) -#define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7) - -#define CONSTRAINT_LEN(C, STR) \ - ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \ - : (C) == 'K' ? 3 \ - : DEFAULT_CONSTRAINT_LEN ((C), (STR))) - -#define CONST_OK_FOR_P(VALUE, STR) \ - ((STR)[1] == '0' ? (VALUE) == 0 \ - : (STR)[1] == '1' ? (VALUE) == 1 \ - : (STR)[1] == '2' ? (VALUE) == 2 \ - : (STR)[1] == '3' ? (VALUE) == 3 \ - : (STR)[1] == '4' ? (VALUE) == 4 \ - : 0) - -#define CONST_OK_FOR_K(VALUE, STR) \ - ((STR)[1] == 'u' \ - ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \ - : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \ - : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \ - : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \ - : 0) \ - : (STR)[1] == 's' \ - ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \ - : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \ - : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \ - : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \ - : 0) \ - : (STR)[1] == 'n' \ - ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \ - : 0) \ - : 0) - -#define CONST_OK_FOR_M(VALUE, STR) \ - ((STR)[1] == '1' ? (VALUE) == 255 \ - : (STR)[1] == '2' ? (VALUE) == 65535 \ - : 0) - -/* The letters I, J, K, L and M in a register constraint string - can be used to stand for particular ranges of immediate operands. - This macro defines what the ranges are. - C is the letter, and VALUE is a constant value. - Return 1 if VALUE is in the range specified by C. - - bfin constant operands are as follows - - J 2**N 5bit imm scaled - Ks7 -64 .. 63 signed 7bit imm - Ku5 0..31 unsigned 5bit imm - Ks4 -8 .. 7 signed 4bit imm - Ks3 -4 .. 3 signed 3bit imm - Ku3 0 .. 7 unsigned 3bit imm - Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n -*/ -#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ - ((C) == 'J' ? (log2constp (VALUE)) \ - : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \ - : (C) == 'L' ? log2constp (~(VALUE)) \ - : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \ - : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \ - : 0) - - /*Constant Output Formats */ -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'H' ? 1 : 0) - -#define EXTRA_CONSTRAINT(VALUE, D) \ - ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0) - -/* `FINALIZE_PIC' - By generating position-independent code, when two different - programs (A and B) share a common library (libC.a), the text of - the library can be shared whether or not the library is linked at - the same address for both programs. In some of these - environments, position-independent code requires not only the use - of different addressing modes, but also special code to enable the - use of these addressing modes. - - The `FINALIZE_PIC' macro serves as a hook to emit these special - codes once the function is being compiled into assembly code, but - not before. (It is not done before, because in the case of - compiling an inline function, it would lead to multiple PIC - prologues being included in functions which used inline functions - and were compiled to assembly language.) */ -#define FINALIZE_PIC do {} while (0) - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section - -#define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) -#define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) - -typedef enum sections { - CODE_DIR, - DATA_DIR, - LAST_SECT_NM -} SECT_ENUM_T; - -typedef enum directives { - LONG_CONST_DIR, - SHORT_CONST_DIR, - BYTE_CONST_DIR, - SPACE_DIR, - INIT_DIR, - LAST_DIR_NM -} DIR_ENUM_T; - -#define TEXT_SECTION_ASM_OP ".text;" -#define DATA_SECTION_ASM_OP ".data;" - -#define ASM_APP_ON "" -#define ASM_APP_OFF "" - -#define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ - do { fputs (".global ", FILE); \ - assemble_name (FILE, NAME); \ - fputc (';',FILE); \ - fputc ('\n',FILE); \ - } while (0) - -#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ - do { \ - fputs (".type ", FILE); \ - assemble_name (FILE, NAME); \ - fputs (", STT_FUNC", FILE); \ - fputc (';',FILE); \ - fputc ('\n',FILE); \ - ASM_OUTPUT_LABEL(FILE, NAME); \ - } while (0) - -#define ASM_OUTPUT_LABEL(FILE, NAME) \ - do { assemble_name (FILE, NAME); \ - fputs (":\n",FILE); \ - } while (0) - -#define ASM_OUTPUT_LABELREF(FILE,NAME) \ - do { fprintf (FILE, "_%s", NAME); \ - } while (0) - -#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ - do { \ - int len = strlen (NAME); \ - char *temp = (char *) alloca (len + 4); \ - temp[0] = 'L'; \ - temp[1] = '_'; \ - strcpy (&temp[2], (NAME)); \ - temp[len + 2] = '_'; \ - temp[len + 3] = 0; \ - (OUTPUT) = (char *) alloca (strlen (NAME) + 13); \ - sprintf (OUTPUT, "_%s$%d", temp, LABELNO); \ - } while (0) - -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ -do { char __buf[256]; \ - fprintf (FILE, "\t.dd\t"); \ - ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ - assemble_name (FILE, __buf); \ - fputc (';', FILE); \ - fputc ('\n', FILE); \ - } while (0) - -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) - -#define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ - do { \ - char __buf[256]; \ - fprintf (FILE, "\t.dd\t"); \ - ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ - assemble_name (FILE, __buf); \ - fputs (" - ", FILE); \ - ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ - assemble_name (FILE, __buf); \ - fputc (';', FILE); \ - fputc ('\n', FILE); \ - } while (0) - -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - do { \ - fprintf (FILE, ".align %d\n", LOG); \ - } while (0) - -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - do { \ - asm_output_skip (FILE, SIZE); \ - } while (0) - -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -do { \ - data_section(); \ - if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ - ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ - ASM_OUTPUT_LABEL (FILE, NAME); \ - fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ - (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ -} while (0) - -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ - do { \ - ASM_GLOBALIZE_LABEL1(FILE,NAME); \ - ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) - -#define ASM_COMMENT_START "//" - -#define FUNCTION_PROFILER(FILE, LABELNO) \ - do {\ - fprintf (FILE, "\tP1.l =LP$%d; P1.h =LP$%d; call mcount;\n", \ - LABELNO, LABELNO);\ - } while(0) - -#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) -#define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) - -extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1; -extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; - -/* This works for GAS and some other assemblers. */ -#define SET_ASM_OP ".set " - -/* Don't know how to order these. UNALIGNED_WORD_ASM_OP is in - dwarf2.out. */ -#define UNALIGNED_WORD_ASM_OP ".4byte" - -/* DBX register number for a given compiler register number */ -#define DBX_REGISTER_NUMBER(REGNO) (REGNO) - -#define SIZE_ASM_OP "\t.size\t" - -#endif /* _BFIN_CONFIG */ diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md deleted file mode 100644 index 348bce90602..00000000000 --- a/gcc/config/bfin/bfin.md +++ /dev/null @@ -1,1902 +0,0 @@ -;;- Machine description for Blackfin for GNU compiler -;; Copyright 2005 Free Software Foundation, Inc. -;; Contributed by Analog Devices. - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 2, or (at your -;; option) any later version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. - -; operand punctuation marks: -; -; X -- integer value printed as log2 -; Y -- integer value printed as log2(~value) - for bitclear -; h -- print half word register, low part -; d -- print half word register, high part -; D -- print operand as dregs pairs -; w -- print operand as accumulator register word (a0w, a1w) -; H -- high part of double mode operand -; T -- byte register representation Oct. 02 2001 - -; constant operand classes -; -; J 2**N 5bit imm scaled -; Ks7 -64 .. 63 signed 7bit imm -; Ku5 0..31 unsigned 5bit imm -; Ks4 -8 .. 7 signed 4bit imm -; Ks3 -4 .. 3 signed 3bit imm -; Ku3 0 .. 7 unsigned 3bit imm -; Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n -; -; register operands -; d (r0..r7) -; a (p0..p5,fp,sp) -; e (a0, a1) -; b (i0..i3) -; f (m0..m3) -; B -; c (i0..i3,m0..m3) CIRCREGS -; C (CC) CCREGS -; - -;; Define constants for hard registers. - -(define_constants - [(REG_R0 0) - (REG_R1 1) - (REG_R2 2) - (REG_R3 3) - (REG_R4 4) - (REG_R5 5) - (REG_R6 6) - (REG_R7 7) - - (REG_P0 8) - (REG_P1 9) - (REG_P2 10) - (REG_P3 11) - (REG_P4 12) - (REG_P5 13) - (REG_P6 14) - (REG_P7 15) - - (REG_SP 14) - (REG_FP 15) - - (REG_I0 16) - (REG_B0 17) - (REG_L0 18) - (REG_I1 19) - (REG_B1 20) - (REG_L1 21) - (REG_I2 22) - (REG_B2 23) - (REG_L2 24) - (REG_I3 25) - (REG_B3 26) - (REG_L3 27) - - (REG_M0 28) - (REG_M1 29) - (REG_M2 30) - (REG_M3 31) - - (REG_A0 32) - (REG_A1 33) - - (REG_CC 34) - (REG_RETS 35) - (REG_RETI 36) - (REG_RETX 37) - (REG_RETN 38) - (REG_RETE 39) - - (REG_ASTAT 40) - (REG_SEQSTAT 41) - (REG_USP 42) - - (REG_ARGP 43)]) - -;; Constants used in UNSPECs and UNSPEC_VOLATILEs. - -(define_constants - [(UNSPEC_CBRANCH_TAKEN 0) - (UNSPEC_CBRANCH_NOPS 1) - (UNSPEC_RETURN 2) - (UNSPEC_MOVE_PIC 3) - (UNSPEC_LIBRARY_OFFSET 4) - (UNSPEC_PUSH_MULTIPLE 5)]) - -(define_constants - [(UNSPEC_VOLATILE_EH_RETURN 0)]) - -(define_attr "type" - "move,mvi,mcld,mcst,dsp32,mult,alu0,shft,brcc,br,call,misc,compare,dummy" - (const_string "misc")) - -;; Scheduling definitions - -(define_automaton "bfin") - -(define_cpu_unit "core" "bfin") - -(define_insn_reservation "alu" 1 - (eq_attr "type" "move,mvi,mcst,dsp32,alu0,shft,brcc,br,call,misc,compare") - "core") - -(define_insn_reservation "imul" 3 - (eq_attr "type" "mult") - "core*3") - -(define_insn_reservation "load" 1 - (eq_attr "type" "mcld") - "core") - -;; Make sure genautomata knows about the maximum latency that can be produced -;; by the adjust_cost function. -(define_insn_reservation "dummy" 5 - (eq_attr "type" "mcld") - "core") - -;; Operand and operator predicates - -(include "predicates.md") - - -;;; FRIO branches have been optimized for code density -;;; this comes at a slight cost of complexity when -;;; a compiler needs to generate branches in the general -;;; case. In order to generate the correct branching -;;; mechanisms the compiler needs keep track of instruction -;;; lengths. The follow table describes how to count instructions -;;; for the FRIO architecture. -;;; -;;; unconditional br are 12-bit imm pcrelative branches *2 -;;; conditional br are 10-bit imm pcrelative branches *2 -;;; brcc 10-bit: -;;; 1024 10-bit imm *2 is 2048 (-1024..1022) -;;; br 12-bit : -;;; 4096 12-bit imm *2 is 8192 (-4096..4094) -;;; NOTE : For brcc we generate instructions such as -;;; if cc jmp; jump.[sl] offset -;;; offset of jump.[sl] is from the jump instruction but -;;; gcc calculates length from the if cc jmp instruction -;;; hence our range is (-4094, 4096) instead of (-4096, 4094) for a br -;;; -;;; The way the (pc) rtx works in these calculations is somewhat odd; -;;; for backward branches it's the address of the current instruction, -;;; for forward branches it's the previously known address of the following -;;; instruction - we have to take this into account by reducing the range -;;; for a forward branch. - -;; Lengths for type "mvi" insns are always defined by the instructions -;; themselves. -(define_attr "length" "" - (cond [(eq_attr "type" "mcld") - (if_then_else (match_operand 1 "effective_address_32bit_p" "") - (const_int 4) (const_int 2)) - - (eq_attr "type" "mcst") - (if_then_else (match_operand 0 "effective_address_32bit_p" "") - (const_int 4) (const_int 2)) - - (eq_attr "type" "move") (const_int 2) - - (eq_attr "type" "dsp32") (const_int 4) - (eq_attr "type" "call") (const_int 4) - - (eq_attr "type" "br") - (if_then_else (and - (le (minus (match_dup 0) (pc)) (const_int 4092)) - (ge (minus (match_dup 0) (pc)) (const_int -4096))) - (const_int 2) - (const_int 4)) - - (eq_attr "type" "brcc") - (cond [(and - (le (minus (match_dup 3) (pc)) (const_int 1020)) - (ge (minus (match_dup 3) (pc)) (const_int -1024))) - (const_int 2) - (and - (le (minus (match_dup 3) (pc)) (const_int 4096)) - (ge (minus (match_dup 3) (pc)) (const_int -4094))) - (const_int 4)] - (const_int 6)) - ] - - (const_int 2))) - -;; Conditional moves - -(define_expand "movsicc" - [(set (match_operand:SI 0 "register_operand" "") - (if_then_else:SI (match_operand 1 "comparison_operator" "") - (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "register_operand" "")))] - "" -{ - operands[1] = bfin_gen_compare (operands[1], SImode); -}) - -(define_insn "*movsicc_insn1" - [(set (match_operand:SI 0 "register_operand" "=da,da,da") - (if_then_else:SI - (eq:BI (match_operand:BI 3 "cc_operand" "C,C,C") - (const_int 0)) - (match_operand:SI 1 "register_operand" "da,0,da") - (match_operand:SI 2 "register_operand" "0,da,da")))] - "" - "@ - if !cc %0 =%1; /* movsicc-1a */ - if cc %0 =%2; /* movsicc-1b */ - if !cc %0 =%1; if cc %0=%2; /* movsicc-1 */" - [(set_attr "length" "2,2,4") - (set_attr "type" "move")]) - -(define_insn "*movsicc_insn2" - [(set (match_operand:SI 0 "register_operand" "=da,da,da") - (if_then_else:SI - (ne:BI (match_operand:BI 3 "cc_operand" "C,C,C") - (const_int 0)) - (match_operand:SI 1 "register_operand" "0,da,da") - (match_operand:SI 2 "register_operand" "da,0,da")))] - "" - "@ - if !cc %0 =%2; /* movsicc-2b */ - if cc %0 =%1; /* movsicc-2a */ - if cc %0 =%1; if !cc %0=%2; /* movsicc-1 */" - [(set_attr "length" "2,2,4") - (set_attr "type" "move")]) - -;; Insns to load HIGH and LO_SUM - -(define_insn "movsi_high" - [(set (match_operand:SI 0 "register_operand" "=x") - (high:SI (match_operand:SI 1 "immediate_operand" "i")))] - "reload_completed" - "%d0 = %d1;" - [(set_attr "type" "mvi") - (set_attr "length" "4")]) - -(define_insn "movstricthi_high" - [(set (match_operand:SI 0 "register_operand" "+x") - (ior:SI (and:SI (match_dup 0) (const_int 65535)) - (match_operand:SI 1 "immediate_operand" "i")))] - "reload_completed" - "%d0 = %d1;" - [(set_attr "type" "mvi") - (set_attr "length" "4")]) - -(define_insn "movsi_low" - [(set (match_operand:SI 0 "register_operand" "=x") - (lo_sum:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "immediate_operand" "i")))] - "reload_completed" - "%h0 = %h2;" - [(set_attr "type" "mvi") - (set_attr "length" "4")]) - -(define_insn "movsi_high_pic" - [(set (match_operand:SI 0 "register_operand" "=x") - (high:SI (unspec:SI [(match_operand:SI 1 "" "")] - UNSPEC_MOVE_PIC)))] - "" - "%d0 = %1@GOT_LOW;" - [(set_attr "type" "mvi") - (set_attr "length" "4")]) - -(define_insn "movsi_low_pic" - [(set (match_operand:SI 0 "register_operand" "=x") - (lo_sum:SI (match_operand:SI 1 "register_operand" "0") - (unspec:SI [(match_operand:SI 2 "" "")] - UNSPEC_MOVE_PIC)))] - "" - "%h0 = %h2@GOT_HIGH;" - [(set_attr "type" "mvi") - (set_attr "length" "4")]) - -;;; Move instructions - -(define_insn_and_split "movdi_insn" - [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r") - (match_operand:DI 1 "general_operand" "iFx,r,mx"))] - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "#" - "reload_completed" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] -{ - rtx lo_half[2], hi_half[2]; - split_di (operands, 2, lo_half, hi_half); - - if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) - { - operands[2] = hi_half[0]; - operands[3] = hi_half[1]; - operands[4] = lo_half[0]; - operands[5] = lo_half[1]; - } - else - { - operands[2] = lo_half[0]; - operands[3] = lo_half[1]; - operands[4] = hi_half[0]; - operands[5] = hi_half[1]; - } -}) - -(define_insn "movbi" - [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,mr,C,d") - (match_operand:BI 1 "general_operand" "x,xKs3,mr,d,d,C"))] - - "" - "@ - %0 = %1; - %0 = %1 (X); - %0 = %1; - %0 = %1; - CC = %1; - %0 = CC;" - [(set_attr "type" "move,mvi,mcld,mcst,compare,compare") - (set_attr "length" "2,2,*,*,2,2")]) - -(define_insn "movpdi" - [(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e") - (match_operand:PDI 1 "general_operand" " e,e,>"))] - "" - "@ - %0 = %1; - %0 = %x1; %0 = %w1; - %w0 = %1; %x0 = %1;" - [(set_attr "type" "move,mcst,mcld")]) - -(define_insn "*pushsi_insn" - [(set (mem:SI (pre_dec:SI (reg:SI REG_SP))) - (match_operand:SI 0 "register_operand" "xy"))] - "" - "[--SP] = %0;" - [(set_attr "type" "mcst") - (set_attr "length" "2")]) - -(define_insn "*popsi_insn" - [(set (match_operand:SI 0 "register_operand" "=xy") - (mem:SI (post_inc:SI (reg:SI REG_SP))))] - "" - "%0 = [SP++];" - [(set_attr "type" "mcld") - (set_attr "length" "2")]) - -;; The first alternative is used to make reload choose a limited register -;; class when faced with a movsi_insn that had its input operand replaced -;; with a PLUS. We generally require fewer secondary reloads this way. -(define_insn "*movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x*y,da,x,x,x,da,mr") - (match_operand:SI 1 "general_operand" "da,x*y,xKs7,xKsh,xKuh,ix,mr,da"))] - - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "@ - %0 = %1; - %0 = %1; - %0 = %1 (X); - %0 = %1 (X); - %0 = %1 (Z); - # - %0 = %1; - %0 = %1;" - [(set_attr "type" "move,move,mvi,mvi,mvi,*,mcld,mcst") - (set_attr "length" "2,2,2,4,4,*,*,*")]) - -(define_insn "*movv2hi_insn" - [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,d,m") - (match_operand:V2HI 1 "general_operand" "d,m,d"))] - - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "%0 = %1;" - [(set_attr "type" "move,mcld,mcst") - (set_attr "length" "2,*,*")]) - -(define_insn "*movhi_insn" - [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr") - (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "@ - %0 = %1; - %0 = %1 (X); - %0 = %1 (X); - %0 = W %1 (X); - W %0 = %1;" - [(set_attr "type" "move,mvi,mvi,mcld,mcst") - (set_attr "length" "2,2,4,*,*")]) - -(define_insn "*movqi_insn" - [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr") - (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))] - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "@ - %0 = %1; - %0 = %1 (X); - %0 = %1 (X); - %0 = B %1 (X); - B %0 = %1;" - [(set_attr "type" "move,mvi,mvi,mcld,mcst") - (set_attr "length" "2,2,4,*,*")]) - -(define_insn "*movsf_insn" - [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr") - (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))] - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "@ - %0 = %1; - # - %0 = %1; - %0 = %1;" - [(set_attr "type" "move,*,mcld,mcst")]) - -(define_insn_and_split "movdf_insn" - [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r") - (match_operand:DF 1 "general_operand" "iFx,r,mx"))] - "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" - "#" - "reload_completed" - [(set (match_dup 2) (match_dup 3)) - (set (match_dup 4) (match_dup 5))] -{ - rtx lo_half[2], hi_half[2]; - split_di (operands, 2, lo_half, hi_half); - - if (reg_overlap_mentioned_p (lo_half[0], hi_half[1])) - { - operands[2] = hi_half[0]; - operands[3] = hi_half[1]; - operands[4] = lo_half[0]; - operands[5] = lo_half[1]; - } - else - { - operands[2] = lo_half[0]; - operands[3] = lo_half[1]; - operands[4] = hi_half[0]; - operands[5] = hi_half[1]; - } -}) - -;; This is the main "hook" for PIC code. When generating -;; PIC, movsi is responsible for determining when the source address -;; needs PIC relocation and appropriately calling legitimize_pic_address -;; to perform the actual relocation. - -(define_expand "movsi" - [(set (match_operand:SI 0 "nonimmediate_operand" "") - (match_operand:SI 1 "general_operand" ""))] - "" - "expand_move (operands, SImode);") - -(define_expand "movv2hi" - [(set (match_operand:V2HI 0 "nonimmediate_operand" "") - (match_operand:V2HI 1 "general_operand" ""))] - "" - "expand_move (operands, V2HImode);") - -(define_expand "movdi" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] - "" - "expand_move (operands, DImode);") - -(define_expand "movsf" - [(set (match_operand:SF 0 "nonimmediate_operand" "") - (match_operand:SF 1 "general_operand" ""))] - "" - "expand_move (operands, SFmode);") - -(define_expand "movdf" - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (match_operand:DF 1 "general_operand" ""))] - "" - "expand_move (operands, DFmode);") - -(define_expand "movhi" - [(set (match_operand:HI 0 "nonimmediate_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" - "expand_move (operands, HImode);") - -(define_expand "movqi" - [(set (match_operand:QI 0 "nonimmediate_operand" "") - (match_operand:QI 1 "general_operand" ""))] - "" - " expand_move (operands, QImode); ") - -;; Some define_splits to break up SI/SFmode loads of immediate constants. - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "symbolic_or_const_operand" ""))] - "reload_completed - /* Always split symbolic operands; split integer constants that are - too large for a single instruction. */ - && (GET_CODE (operands[1]) != CONST_INT - || (INTVAL (operands[1]) < -32768 - || INTVAL (operands[1]) >= 65536 - || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))" - [(set (match_dup 0) (high:SI (match_dup 1))) - (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))] -{ - if (GET_CODE (operands[1]) == CONST_INT - && split_load_immediate (operands)) - DONE; - /* ??? Do something about TARGET_LOW_64K. */ -}) - -(define_split - [(set (match_operand:SF 0 "register_operand" "") - (match_operand:SF 1 "immediate_operand" ""))] - "reload_completed" - [(set (match_dup 2) (high:SI (match_dup 3))) - (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))] -{ - long values; - REAL_VALUE_TYPE value; - - if (GET_CODE (operands[1]) != CONST_DOUBLE) - abort (); - - REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]); - REAL_VALUE_TO_TARGET_SINGLE (value, values); - - operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0])); - operands[3] = GEN_INT (trunc_int_for_mode (values, SImode)); - if (values >= -32768 && values < 65536) - { - emit_move_insn (operands[2], operands[3]); - DONE; - } - if (split_load_immediate (operands + 2)) - DONE; -}) - -;; Sadly, this can't be a proper named movstrict pattern, since the compiler -;; expects to be able to use registers for operand 1. -;; Note that the asm instruction is defined by the manual to take an unsigned -;; constant, but it doesn't matter to the assembler, and the compiler only -;; deals with sign-extended constants. Hence "Ksh". -(define_insn "*movstricthi" - [(set (strict_low_part (match_operand:HI 0 "register_operand" "+x")) - (match_operand:HI 1 "immediate_operand" "Ksh"))] - "" - "%h0 = %1;" - [(set_attr "type" "mvi") - (set_attr "length" "4")]) - -;; Sign and zero extensions - -(define_insn "extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=d, d") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] - "" - "@ - %0 = %h1 (X); - %0 = W %h1 (X);" - [(set_attr "type" "alu0,mcld")]) - -(define_insn "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "=d, d") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))] - "" - "@ - %0 = %h1 (Z); - %0 = W%h1 (Z);" - [(set_attr "type" "alu0,mcld")]) - -(define_insn "zero_extendbisi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))] - "" - "%0 = %1;" - [(set_attr "type" "compare")]) - -(define_insn "extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=d, d") - (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] - "" - "@ - %0 = B %1 (X); - %0 = %T1 (X);" - [(set_attr "type" "mcld,alu0")]) - -(define_insn "extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=d, d") - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] - "" - "@ - %0 = B %1 (X); - %0 = %T1 (X);" - [(set_attr "type" "mcld,alu0")]) - - -(define_insn "zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=d, d") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] - "" - "@ - %0 = B %1 (Z); - %0 = %T1 (Z);" - [(set_attr "type" "mcld,alu0")]) - - -(define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=d, d") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))] - "" - "@ - %0 = B %1 (Z); - %0 = %T1 (Z);" - [(set_attr "type" "mcld,alu0")]) - -;; DImode logical operations - -(define_code_macro any_logical [and ior xor]) -(define_code_attr optab [(and "and") - (ior "ior") - (xor "xor")]) -(define_code_attr op [(and "&") - (ior "|") - (xor "^")]) -(define_code_attr high_result [(and "0") - (ior "%H1") - (xor "%H1")]) - -(define_insn "<optab>di3" - [(set (match_operand:DI 0 "register_operand" "=d") - (any_logical:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "register_operand" "d")))] - "" - "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;" - [(set_attr "length" "4")]) - -(define_insn "*<optab>di_zesidi_di" - [(set (match_operand:DI 0 "register_operand" "=d") - (any_logical:DI (zero_extend:DI - (match_operand:SI 2 "register_operand" "d")) - (match_operand:DI 1 "register_operand" "d")))] - "" - "%0 = %1 <op> %2;\\n\\t%H0 = <high_result>;" - [(set_attr "length" "4")]) - -(define_insn "*<optab>di_sesdi_di" - [(set (match_operand:DI 0 "register_operand" "=d") - (any_logical:DI (sign_extend:DI - (match_operand:SI 2 "register_operand" "d")) - (match_operand:DI 1 "register_operand" "0"))) - (clobber (match_scratch:SI 3 "=&d"))] - "" - "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;" - [(set_attr "length" "8")]) - -(define_insn "negdi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (neg:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (match_scratch:SI 2 "=&d")) - (clobber (reg:CC REG_CC))] - "" - "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;" - [(set_attr "length" "16")]) - -(define_insn "one_cmpldi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (not:DI (match_operand:DI 1 "register_operand" "d")))] - "" - "%0 = ~%1;\\n\\t%H0 = ~%H1;" - [(set_attr "length" "4")]) - -;; DImode zero and sign extend patterns - -(define_insn_and_split "zero_extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] - "" - "#" - "reload_completed" - [(set (match_dup 3) (const_int 0))] -{ - split_di (operands, 1, operands + 2, operands + 3); - if (REGNO (operands[0]) != REGNO (operands[1])) - emit_move_insn (operands[2], operands[1]); -}) - -(define_insn "zero_extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] - "" - "%0 = %T1 (Z);\\n\\t%H0 = 0;" - [(set_attr "length" "4")]) - -(define_insn "zero_extendhidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] - "" - "%0 = %h1 (Z);\\n\\t%H0 = 0;" - [(set_attr "length" "4")]) - -(define_insn_and_split "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] - "" - "#" - "reload_completed" - [(set (match_dup 3) (match_dup 1)) - (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] -{ - split_di (operands, 1, operands + 2, operands + 3); - if (REGNO (operands[0]) != REGNO (operands[1])) - emit_move_insn (operands[2], operands[1]); -}) - -(define_insn_and_split "extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] - "" - "#" - "reload_completed" - [(set (match_dup 2) (sign_extend:SI (match_dup 1))) - (set (match_dup 3) (sign_extend:SI (match_dup 1))) - (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] -{ - split_di (operands, 1, operands + 2, operands + 3); -}) - -(define_insn_and_split "extendhidi2" - [(set (match_operand:DI 0 "register_operand" "=d") - (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] - "" - "#" - "reload_completed" - [(set (match_dup 2) (sign_extend:SI (match_dup 1))) - (set (match_dup 3) (sign_extend:SI (match_dup 1))) - (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))] -{ - split_di (operands, 1, operands + 2, operands + 3); -}) - -;; DImode arithmetic operations - -(define_insn "adddi3" - [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d") - (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0") - (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d"))) - (clobber (match_scratch:SI 3 "=&d,&d,&d")) - (clobber (reg:CC 34))] - "" - "@ - %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3; - %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3; - %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;" - [(set_attr "type" "alu0") - (set_attr "length" "10,8,10")]) - -(define_insn "subdi3" - [(set (match_operand:DI 0 "register_operand" "=&d") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "register_operand" "d"))) - (clobber (reg:CC 34))] - "" - "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" - [(set_attr "length" "10")]) - -(define_insn "*subdi_di_zesidi" - [(set (match_operand:DI 0 "register_operand" "=d") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (zero_extend:DI - (match_operand:SI 2 "register_operand" "d")))) - (clobber (match_scratch:SI 3 "=&d")) - (clobber (reg:CC 34))] - "" - "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;" - [(set_attr "length" "10")]) - -(define_insn "*subdi_zesidi_di" - [(set (match_operand:DI 0 "register_operand" "=d") - (minus:DI (zero_extend:DI - (match_operand:SI 2 "register_operand" "d")) - (match_operand:DI 1 "register_operand" "0"))) - (clobber (match_scratch:SI 3 "=&d")) - (clobber (reg:CC 34))] - "" - "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1" - [(set_attr "length" "12")]) - -(define_insn "*subdi_di_sesidi" - [(set (match_operand:DI 0 "register_operand" "=d") - (minus:DI (match_operand:DI 1 "register_operand" "0") - (sign_extend:DI - (match_operand:SI 2 "register_operand" "d")))) - (clobber (match_scratch:SI 3 "=&d")) - (clobber (reg:CC 34))] - "" - "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" - [(set_attr "length" "14")]) - -(define_insn "*subdi_sesidi_di" - [(set (match_operand:DI 0 "register_operand" "=d") - (minus:DI (sign_extend:DI - (match_operand:SI 2 "register_operand" "d")) - (match_operand:DI 1 "register_operand" "0"))) - (clobber (match_scratch:SI 3 "=&d")) - (clobber (reg:CC 34))] - "" - "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:" - [(set_attr "length" "14")]) - -;; Combined shift/add instructions - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a,d") - (ashift:SI (plus:SI (match_operand:SI 1 "register_operand" "%0,0") - (match_operand:SI 2 "register_operand" "a,d")) - (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))] - "" - "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */ - [(set_attr "type" "alu0")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a") - (plus:SI (match_operand:SI 1 "register_operand" "a") - (mult:SI (match_operand:SI 2 "register_operand" "a") - (match_operand:SI 3 "scale_by_operand" "i"))))] - "" - "%0 = %1 + (%2 << %X3);" - [(set_attr "type" "alu0")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a") - (plus:SI (match_operand:SI 1 "register_operand" "a") - (ashift:SI (match_operand:SI 2 "register_operand" "a") - (match_operand:SI 3 "pos_scale_operand" "i"))))] - "" - "%0 = %1 + (%2 << %3);" - [(set_attr "type" "alu0")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "a") - (match_operand:SI 2 "scale_by_operand" "i")) - (match_operand:SI 3 "register_operand" "a")))] - "" - "%0 = %3 + (%1 << %X2);" - [(set_attr "type" "alu0")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a") - (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "a") - (match_operand:SI 2 "pos_scale_operand" "i")) - (match_operand:SI 3 "register_operand" "a")))] - "" - "%0 = %3 + (%1 << %2);" - [(set_attr "type" "alu0")]) - -(define_insn "mulhisi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%d")) - (sign_extend:SI (match_operand:HI 2 "register_operand" "d"))))] - "" - "%0 = %h1 * %h2 (IS);" - [(set_attr "type" "dsp32")]) - -(define_insn "umulhisi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%d")) - (zero_extend:SI (match_operand:HI 2 "register_operand" "d"))))] - "" - "%0 = %h1 * %h2 (FU);" - [(set_attr "type" "dsp32")]) - -;; The processor also supports ireg += mreg or ireg -= mreg, but these -;; are unusable if we don't ensure that the corresponding lreg is zero. -;; The same applies to the add/subtract constant versions involving -;; iregs - -(define_insn "addsi3" - [(set (match_operand:SI 0 "register_operand" "=ad,a,d") - (plus:SI (match_operand:SI 1 "register_operand" "%0, a,d") - (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))] - "" - "@ - %0 += %2; - %0 = %1 + %2; - %0 = %1 + %2;" - [(set_attr "type" "alu0") - (set_attr "length" "2,2,2")]) - -(define_expand "subsi3" - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "reg_or_7bit_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=da,d,a") - (minus:SI (match_operand:SI 1 "register_operand" "0,d,0") - (match_operand:SI 2 "reg_or_7bit_operand" "Ks7,d,a")))] - "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -64" -{ - static const char *const strings_subsi3[] = { - "%0 += -%2;", - "%0 = %1 - %2;", - "%0 -= %2;", - }; - - if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) { - rtx tmp_op = operands[2]; - operands[2] = GEN_INT (-INTVAL (operands[2])); - output_asm_insn ("%0 += %2;", operands); - operands[2] = tmp_op; - return ""; - } - - return strings_subsi3[which_alternative]; -} - [(set_attr "type" "alu0")]) - -;; Bit test instructions - -(define_insn "*not_bittst" - [(set (match_operand:BI 0 "cc_operand" "=C") - (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") - (const_int 1) - (match_operand:SI 2 "immediate_operand" "Ku5")) - (const_int 0)))] - "" - "cc = !BITTST (%1,%2);" - [(set_attr "type" "alu0")]) - -(define_insn "*bittst" - [(set (match_operand:BI 0 "cc_operand" "=C") - (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") - (const_int 1) - (match_operand:SI 2 "immediate_operand" "Ku5")) - (const_int 0)))] - "" - "cc = BITTST (%1,%2);" - [(set_attr "type" "alu0")]) - -(define_insn_and_split "*bit_extract" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extract:SI (match_operand:SI 1 "register_operand" "d") - (const_int 1) - (match_operand:SI 2 "immediate_operand" "Ku5"))) - (clobber (reg:BI REG_CC))] - "" - "#" - "" - [(set (reg:BI REG_CC) - (ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) - (const_int 0))) - (set (match_dup 0) - (ne:SI (reg:BI REG_CC) (const_int 0)))]) - -(define_insn_and_split "*not_bit_extract" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extract:SI (not:SI (match_operand:SI 1 "register_operand" "d")) - (const_int 1) - (match_operand:SI 2 "immediate_operand" "Ku5"))) - (clobber (reg:BI REG_CC))] - "" - "#" - "" - [(set (reg:BI REG_CC) - (eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2)) - (const_int 0))) - (set (match_dup 0) - (ne:SI (reg:BI REG_CC) (const_int 0)))]) - -(define_insn "*andsi_insn" - [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") - (and:SI (match_operand:SI 1 "register_operand" "%0,d,d,d") - (match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))] - "" - "@ - BITCLR (%0,%Y2); - %0 = %T1 (Z); - %0 = %h1 (Z); - %0 = %1 & %2;" - [(set_attr "type" "alu0")]) - -(define_expand "andsi3" - [(set (match_operand:SI 0 "register_operand" "") - (and:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "general_operand" "")))] - "" -{ - if (highbits_operand (operands[2], SImode)) - { - operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2]))); - emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2])); - emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2])); - DONE; - } - if (! rhs_andsi3_operand (operands[2], SImode)) - operands[2] = force_reg (SImode, operands[2]); -}) - -(define_insn "iorsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (ior:SI (match_operand:SI 1 "register_operand" "%0,d") - (match_operand:SI 2 "regorlog2_operand" "J,d")))] - "" - "@ - BITSET (%0, %X2); - %0 = %1 | %2;" - [(set_attr "type" "alu0")]) - -(define_insn "xorsi3" - [(set (match_operand:SI 0 "register_operand" "=d,d") - (xor:SI (match_operand:SI 1 "register_operand" "%0,d") - (match_operand:SI 2 "regorlog2_operand" "J,d")))] - "" - "@ - BITTGL (%0, %X2); - %0 = %1 ^ %2;" - [(set_attr "type" "alu0")]) - -(define_insn "smaxsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (smax:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")))] - "" - "%0 =max(%1,%2);" - [(set_attr "type" "dsp32")]) - -(define_insn "sminsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (smin:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d")))] - "" - "%0 =min(%1,%2);" - [(set_attr "type" "dsp32")]) - -(define_insn "abssi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (abs:SI (match_operand:SI 1 "register_operand" " d")))] - "" - "%0 =abs %1;" - [(set_attr "type" "dsp32")]) - - -(define_insn "negsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (neg:SI (match_operand:SI 1 "register_operand" " d")))] - "" - "%0 =-%1;" - [(set_attr "type" "alu0")]) - -(define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (not:SI (match_operand:SI 1 "register_operand" " d")))] - "" - "%0 =~%1;" - [(set_attr "type" "alu0")]) - -(define_insn "mulsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (mult:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "register_operand" "d")))] - "" - "%0 *=%2;" - [(set_attr "type" "mult")]) - -(define_expand "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "") - (ashift:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")))] - "" -{ - if (GET_CODE (operands[2]) == CONST_INT - && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) - { - emit_insn (gen_movsi (operands[0], const0_rtx)); - DONE; - } -}) - -(define_insn_and_split "*ashlsi3_insn" - [(set (match_operand:SI 0 "register_operand" "=d,a,a,a") - (ashift:SI (match_operand:SI 1 "register_operand" "0,a,a,a") - (match_operand:SI 2 "nonmemory_operand" "dKu5,P1,P2,?P3P4")))] - "" - "@ - %0 <<= %2; - %0 = %1 + %1; - %0 = %1 << %2; - #" - "PREG_P (operands[0]) && INTVAL (operands[2]) > 2" - [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2))) - (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))] - "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);" - [(set_attr "type" "shft")]) - -(define_insn "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "dKu5")))] - "" - "%0 >>>= %2;" - [(set_attr "type" "shft")]) - -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=d,a") - (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0,a") - (match_operand:SI 2 "nonmemory_operand" "dKu5,P1P2")))] - "" - "@ - %0 >>= %2; - %0 = %1 >> %2;" - [(set_attr "type" "shft")]) - -;; A pattern to reload the equivalent of -;; (set (Dreg) (plus (FP) (large_constant))) -;; or -;; (set (dagreg) (plus (FP) (arbitrary_constant))) -;; using a scratch register -(define_expand "reload_insi" - [(parallel [(set (match_operand:SI 0 "register_operand" "=w") - (match_operand:SI 1 "fp_plus_const_operand" "")) - (clobber (match_operand:SI 2 "register_operand" "=&a"))])] - "" -{ - rtx fp_op = XEXP (operands[1], 0); - rtx const_op = XEXP (operands[1], 1); - rtx primary = operands[0]; - rtx scratch = operands[2]; - - emit_move_insn (scratch, const_op); - emit_insn (gen_addsi3 (scratch, scratch, fp_op)); - emit_move_insn (primary, scratch); - DONE; -}) - -;; Jump instructions - -(define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] - "" -{ - if (get_attr_length (insn) == 2) - return "jump.s %0;"; - else - return "jump.l %0;"; -} - [(set_attr "type" "br")]) - -(define_insn "indirect_jump" - [(set (pc) - (match_operand:SI 0 "register_operand" "a"))] - "" - "jump (%0);" - [(set_attr "type" "misc")]) - -(define_expand "tablejump" - [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "a")) - (use (label_ref (match_operand 1 "" "")))])] - "" -{ - /* In PIC mode, the table entries are stored PC relative. - Convert the relative address to an absolute address. */ - if (flag_pic) - { - rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]); - - operands[0] = expand_simple_binop (Pmode, PLUS, operands[0], - op1, NULL_RTX, 0, OPTAB_DIRECT); - } -}) - -(define_insn "*tablejump_internal" - [(set (pc) (match_operand:SI 0 "register_operand" "a")) - (use (label_ref (match_operand 1 "" "")))] - "" - "jump (%0);" - [(set_attr "type" "misc")]) - -;; Call instructions.. - -(define_expand "call" - [(call (match_operand:SI 0 "" "") - (match_operand 1 "" ""))] - "" - "bfin_expand_call (NULL_RTX, operands[0], operands[1], 0); DONE;") - -(define_expand "sibcall" - [(parallel [(call (match_operand:SI 0 "" "") - (match_operand 1 "" "")) - (return)])] - "" - "bfin_expand_call (NULL_RTX, operands[0], operands[1], 1); DONE;") - -(define_expand "call_value" - [(set (match_operand 0 "register_operand" "") - (call (match_operand:SI 1 "" "") - (match_operand 2 "" "")))] - "" - "bfin_expand_call (operands[0], operands[1], operands[2], 0); DONE;") - -(define_expand "sibcall_value" - [(parallel [(set (match_operand 0 "register_operand" "") - (call (match_operand:SI 1 "" "") - (match_operand 2 "" ""))) - (return)])] - "" - "bfin_expand_call (operands[0], operands[1], operands[2], 1); DONE;") - -(define_insn "*call_insn" - [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "a,Q")) - (match_operand 1 "general_operand" "g,g"))] - "! SIBLING_CALL_P (insn) - && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)" - "@ - call (%0); - call %G0;" - [(set_attr "type" "call") - (set_attr "length" "2,4")]) - -(define_insn "*sibcall_insn" - [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "z,Q")) - (match_operand 1 "general_operand" "g,g")) - (return)] - "SIBLING_CALL_P (insn) - && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)" - "@ - jump (%0); - jump.l %G0;" - [(set_attr "type" "br") - (set_attr "length" "2,4")]) - -(define_insn "*call_value_insn" - [(set (match_operand 0 "register_operand" "=d,d") - (call (mem:SI (match_operand:SI 1 "call_insn_operand" "a,Q")) - (match_operand 2 "general_operand" "g,g")))] - "! SIBLING_CALL_P (insn) - && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)" - "@ - call (%1); - call %G1;" - [(set_attr "type" "call") - (set_attr "length" "2,4")]) - -(define_insn "*sibcall_value_insn" - [(set (match_operand 0 "register_operand" "=d,d") - (call (mem:SI (match_operand:SI 1 "call_insn_operand" "z,Q")) - (match_operand 2 "general_operand" "g,g"))) - (return)] - "SIBLING_CALL_P (insn) - && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)" - "@ - jump (%1); - jump.l %G1;" - [(set_attr "type" "br") - (set_attr "length" "2,4")]) - -;; Block move patterns - -;; We cheat. This copies one more word than operand 2 indicates. - -(define_insn "rep_movsi" - [(set (match_operand:SI 0 "register_operand" "=&a") - (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") - (ashift:SI (match_operand:SI 2 "register_operand" "a") - (const_int 2))) - (const_int 4))) - (set (match_operand:SI 1 "register_operand" "=&b") - (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") - (ashift:SI (match_dup 2) (const_int 2))) - (const_int 4))) - (set (mem:BLK (match_dup 3)) - (mem:BLK (match_dup 4))) - (use (match_dup 2)) - (clobber (match_scratch:HI 5 "=&d"))] - "" - "lsetup (1f, 1f) LC1 = %2; %5 = [%4++]; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;" - [(set_attr "type" "misc") - (set_attr "length" "16")]) - -(define_insn "rep_movhi" - [(set (match_operand:SI 0 "register_operand" "=&a") - (plus:SI (plus:SI (match_operand:SI 3 "register_operand" "0") - (ashift:SI (match_operand:SI 2 "register_operand" "a") - (const_int 1))) - (const_int 2))) - (set (match_operand:SI 1 "register_operand" "=&b") - (plus:SI (plus:SI (match_operand:SI 4 "register_operand" "1") - (ashift:SI (match_dup 2) (const_int 1))) - (const_int 2))) - (set (mem:BLK (match_dup 3)) - (mem:BLK (match_dup 4))) - (use (match_dup 2)) - (clobber (match_scratch:HI 5 "=&d"))] - "" - "lsetup (1f, 1f) LC1 = %2; %h5 = W[%4++]; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;" - [(set_attr "type" "misc") - (set_attr "length" "16")]) - -(define_expand "movstrsi" - [(match_operand:BLK 0 "general_operand" "") - (match_operand:BLK 1 "general_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")] - "" -{ - if (bfin_expand_strmov (operands[0], operands[1], operands[2], operands[3])) - DONE; - FAIL; -}) - -;; Conditional branch patterns -;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu - -;; The only outcome of this pattern is that global variables -;; bfin_compare_op[01] are set for use in bcond patterns. - -(define_expand "cmpbi" - [(set (cc0) (compare (match_operand:BI 0 "register_operand" "") - (match_operand:BI 1 "immediate_operand" "")))] - "" -{ - bfin_compare_op0 = operands[0]; - bfin_compare_op1 = operands[1]; - DONE; -}) - -(define_expand "cmpsi" - [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "nonmemory_operand" "")))] - "" -{ - bfin_compare_op0 = operands[0]; - bfin_compare_op1 = operands[1]; - DONE; -}) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C,C") - (eq:BI (match_operand:SI 1 "register_operand" "d,a") - (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))] - "" - "cc =%1==%2;" - [(set_attr "type" "compare")]) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C,C") - (ne:BI (match_operand:SI 1 "register_operand" "d,a") - (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))] - "0" - "cc =%1!=%2;" - [(set_attr "type" "compare")]) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C,C") - (lt:BI (match_operand:SI 1 "register_operand" "d,a") - (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))] - "" - "cc =%1<%2;" - [(set_attr "type" "compare")]) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C,C") - (le:BI (match_operand:SI 1 "register_operand" "d,a") - (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))] - "" - "cc =%1<=%2;" - [(set_attr "type" "compare")]) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C,C") - (leu:BI (match_operand:SI 1 "register_operand" "d,a") - (match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))] - "" - "cc =%1<=%2 (iu);" - [(set_attr "type" "compare")]) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C,C") - (ltu:BI (match_operand:SI 1 "register_operand" "d,a") - (match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))] - "" - "cc =%1<%2 (iu);" - [(set_attr "type" "compare")]) - -(define_expand "beq" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; - operands[1] = bfin_cc_rtx; /* hard register: CC */ - operands[2] = gen_rtx_EQ (BImode, op0, op1); - /* If we have a BImode input, then we already have a compare result, and - do not need to emit another comparison. */ - if (GET_MODE (bfin_compare_op0) == BImode) - { - if (bfin_compare_op1 == const0_rtx) - { - emit_insn (gen_cbranchbi4 (operands[2], op0, op1, - operands[0])); - DONE; - } - else - abort (); - } - - operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); -}) - -(define_expand "bne" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1; - /* If we have a BImode input, then we already have a compare result, and - do not need to emit another comparison. */ - if (GET_MODE (bfin_compare_op0) == BImode) - { - if (bfin_compare_op1 == const0_rtx) - { - rtx cmp = gen_rtx_NE (BImode, op0, op1); - emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0])); - DONE; - } - else - abort (); - } - - operands[1] = bfin_cc_rtx; /* hard register: CC */ - operands[2] = gen_rtx_EQ (BImode, op0, op1); - operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); -}) - -(define_expand "bgt" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); -}) - -(define_expand "bgtu" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); -}) - -(define_expand "blt" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); -}) - -(define_expand "bltu" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); -}) - - -(define_expand "bge" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); -}) - -(define_expand "bgeu" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx); -}) - -(define_expand "ble" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); -}) - -(define_expand "bleu" - [(set (match_dup 1) (match_dup 2)) - (set (pc) - (if_then_else (match_dup 3) - (label_ref (match_operand 0 "" "")) - (pc))) - ] - "" -{ - operands[1] = bfin_cc_rtx; - operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1); - operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx); -}) - -(define_insn "cbranchbi4" - [(set (pc) - (if_then_else - (match_operator 0 "bfin_cbranch_operator" - [(match_operand:BI 1 "cc_operand" "C") - (match_operand:BI 2 "immediate_operand" "P0")]) - (label_ref (match_operand 3 "" "")) - (pc)))] - "" -{ - asm_conditional_branch (insn, operands, 0, 0); - return ""; -} - [(set_attr "type" "brcc")]) - -;; Special cbranch patterns to deal with the speculative load problem - see -;; bfin_reorg for details. - -(define_insn "cbranch_predicted_taken" - [(set (pc) - (if_then_else - (match_operator 0 "bfin_cbranch_operator" - [(match_operand:BI 1 "cc_operand" "C") - (match_operand:BI 2 "immediate_operand" "P0")]) - (label_ref (match_operand 3 "" "")) - (pc))) - (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)] - "" -{ - asm_conditional_branch (insn, operands, 0, 1); - return ""; -} - [(set_attr "type" "brcc")]) - -(define_insn "cbranch_with_nops" - [(set (pc) - (if_then_else - (match_operator 0 "bfin_cbranch_operator" - [(match_operand:BI 1 "cc_operand" "C") - (match_operand:BI 2 "immediate_operand" "P0")]) - (label_ref (match_operand 3 "" "")) - (pc))) - (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)] - "reload_completed" -{ - asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0); - return ""; -} - [(set_attr "type" "brcc") - (set_attr "length" "6")]) - -;; setcc insns. */ -(define_expand "seq" - [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3))) - (set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_dup 1) (const_int 0)))] - "" -{ - operands[2] = bfin_compare_op0; - operands[3] = bfin_compare_op1; - operands[1] = bfin_cc_rtx; -}) - -(define_expand "slt" - [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3))) - (set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_dup 1) (const_int 0)))] - "" -{ - operands[2] = bfin_compare_op0; - operands[3] = bfin_compare_op1; - operands[1] = bfin_cc_rtx; -}) - -(define_expand "sle" - [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3))) - (set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_dup 1) (const_int 0)))] - "" -{ - operands[2] = bfin_compare_op0; - operands[3] = bfin_compare_op1; - operands[1] = bfin_cc_rtx; -}) - -(define_expand "sltu" - [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3))) - (set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_dup 1) (const_int 0)))] - "" -{ - operands[2] = bfin_compare_op0; - operands[3] = bfin_compare_op1; - operands[1] = bfin_cc_rtx; -}) - -(define_expand "sleu" - [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3))) - (set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_dup 1) (const_int 0)))] - "" -{ - operands[2] = bfin_compare_op0; - operands[3] = bfin_compare_op1; - operands[1] = bfin_cc_rtx; -}) - -(define_insn "nop" - [(const_int 0)] - "" - "nop;") - -;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "movsibi" - [(set (match_operand:BI 0 "cc_operand" "=C") - (ne:BI (match_operand:SI 1 "register_operand" "d") - (const_int 0)))] - "" - "CC = %1;" - [(set_attr "length" "2")]) - -(define_insn "movbisi" - [(set (match_operand:SI 0 "register_operand" "=d") - (ne:SI (match_operand:BI 1 "cc_operand" "C") - (const_int 0)))] - "" - "%0 = CC;" - [(set_attr "length" "2")]) - -(define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C") - (eq:BI (match_operand:BI 1 "cc_operand" " 0") - (const_int 0)))] - "" - "%0 = ! %0;" /* NOT CC;" */ - [(set_attr "type" "compare")]) - -;; Vector and DSP insns - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") - (const_int 24)) - (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") - (const_int 8))))] - "" - "%0 = ALIGN8(%1, %2);" - [(set_attr "type" "dsp32")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") - (const_int 16)) - (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") - (const_int 16))))] - "" - "%0 = ALIGN16(%1, %2);" - [(set_attr "type" "dsp32")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") - (const_int 8)) - (lshiftrt:SI (match_operand:SI 2 "register_operand" "d") - (const_int 24))))] - "" - "%0 = ALIGN24(%1, %2);" - [(set_attr "type" "dsp32")]) - -;; Prologue and epilogue. - -(define_expand "prologue" - [(const_int 1)] - "" - "bfin_expand_prologue (); DONE;") - -(define_expand "epilogue" - [(const_int 1)] - "" - "bfin_expand_epilogue (1, 0); DONE;") - -(define_expand "sibcall_epilogue" - [(const_int 1)] - "" - "bfin_expand_epilogue (0, 0); DONE;") - -(define_expand "eh_return" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "")] - UNSPEC_VOLATILE_EH_RETURN)] - "" -{ - emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]); - emit_insn (gen_eh_return_internal ()); - emit_barrier (); -}) - -(define_insn_and_split "eh_return_internal" - [(unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN)] - "" - "#" - "reload_completed" - [(const_int 1)] - "bfin_expand_epilogue (1, 1); DONE;") - -(define_insn "link" - [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS)) - (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP)) - (set (reg:SI REG_FP) - (plus:SI (reg:SI REG_SP) (const_int -8))) - (set (reg:SI REG_SP) - (plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))] - "" - "LINK %Z0;" - [(set_attr "length" "4")]) - -(define_insn "unlink" - [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP))) - (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4)))) - (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))] - "" - "UNLINK;" - [(set_attr "length" "4")]) - -;; This pattern is slightly clumsy. The stack adjust must be the final SET in -;; the pattern, otherwise dwarf2out becomes very confused about which reg goes -;; where on the stack, since it goes through all elements of the parallel in -;; sequence. -(define_insn "push_multiple" - [(match_parallel 0 "push_multiple_operation" - [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])] - "" -{ - output_push_multiple (insn, operands); - return ""; -}) - -(define_insn "pop_multiple" - [(match_parallel 0 "pop_multiple_operation" - [(set (reg:SI REG_SP) - (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])] - "" -{ - output_pop_multiple (insn, operands); - return ""; -}) - -(define_insn "return_internal" - [(return) - (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)] - "reload_completed" -{ - switch (INTVAL (operands[0])) - { - case EXCPT_HANDLER: - return "rtx;"; - case NMI_HANDLER: - return "rtn;"; - case INTERRUPT_HANDLER: - return "rti;"; - case SUBROUTINE: - return "rts;"; - } - gcc_unreachable (); -}) - -;;; Vector instructions - -(define_insn "addv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (plus:V2HI (match_operand:V2HI 1 "register_operand" "d") - (match_operand:V2HI 2 "register_operand" "d")))] - "" - "%0 = %1 +|+ %2;" - [(set_attr "type" "dsp32")]) - -(define_insn "subv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (minus:V2HI (match_operand:V2HI 1 "register_operand" "d") - (match_operand:V2HI 2 "register_operand" "d")))] - "" - "%0 = %1 -|- %2;" - [(set_attr "type" "dsp32")]) - -(define_insn "sminv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (smin:V2HI (match_operand:V2HI 1 "register_operand" "d") - (match_operand:V2HI 2 "register_operand" "d")))] - "" - "%0 = MIN (%1, %2) (V);" - [(set_attr "type" "dsp32")]) - -(define_insn "smaxv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (smax:V2HI (match_operand:V2HI 1 "register_operand" "d") - (match_operand:V2HI 2 "register_operand" "d")))] - "" - "%0 = MAX (%1, %2) (V);" - [(set_attr "type" "dsp32")]) - -(define_insn "mulv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") - (match_operand:V2HI 2 "register_operand" "d")))] - "" - "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS);" - [(set_attr "type" "dsp32")]) - -(define_insn "negv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))] - "" - "%0 = - %1 (V);" - [(set_attr "type" "dsp32")]) - -(define_insn "absv2hi" - [(set (match_operand:V2HI 0 "register_operand" "=d") - (abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))] - "" - "%0 = ABS %1 (V);" - [(set_attr "type" "dsp32")]) - diff --git a/gcc/config/bfin/bfin.opt b/gcc/config/bfin/bfin.opt deleted file mode 100644 index 827947d5e6a..00000000000 --- a/gcc/config/bfin/bfin.opt +++ /dev/null @@ -1,40 +0,0 @@ -; Options for the Blackfin port of the compiler -; -; Copyright (C) 2005 Free Software Foundation, Inc. -; -; This file is part of GCC. -; -; GCC is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License as published by the Free -; Software Foundation; either version 2, or (at your option) any later -; version. -; -; GCC is distributed in the hope that it will be useful, but WITHOUT -; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -; License for more details. -; -; You should have received a copy of the GNU General Public License -; along with GCC; see the file COPYING. If not, write to the Free -; Software Foundation, 59 Temple Place - Suite 330, Boston, MA -; 02111-1307, USA. - -momit-leaf-frame-pointer -Target Report Mask(OMIT_LEAF_FRAME_POINTER) -Omit frame pointer for leaf functions - -mlow64k -Target Report Mask(LOW_64K) -Program is entirely located in low 64k of memory. - -mcsync -Target Report Mask(CSYNC) -Avoid speculative loads by inserting CSYNC or equivalent - -mid-shared-library -Target Report Mask(ID_SHARED_LIBRARY) -Enabled ID based shared library - -mshared-library-id= -Target RejectNegative Joined UInteger -ID of shared library to build diff --git a/gcc/config/bfin/crti.s b/gcc/config/bfin/crti.s deleted file mode 100644 index 69e67007091..00000000000 --- a/gcc/config/bfin/crti.s +++ /dev/null @@ -1,47 +0,0 @@ -/* Specialized code needed to support construction and destruction of - file-scope objects in C++ and Java code, and to support exception handling. - Copyright (C) 2005 Free Software Foundation, Inc. - Contributed by Analog Devices. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* As a special exception, if you link this library with files - compiled with GCC to produce an executable, this does not cause - the resulting executable to be covered by the GNU General Public License. - This exception does not however invalidate any other reasons why - the executable file might be covered by the GNU General Public License. */ - -/* - * This file just supplies function prologues for the .init and .fini - * sections. It is linked in before crtbegin.o. - */ - - .file "crti.o" - .ident "GNU C crti.o" - - .section .init - .globl _init - .type _init,@function -_init: - LINK 0; - - .section .fini - .globl _fini - .type _fini,@function -_fini: - LINK 0; diff --git a/gcc/config/bfin/crtn.s b/gcc/config/bfin/crtn.s deleted file mode 100644 index fb25b77c5f9..00000000000 --- a/gcc/config/bfin/crtn.s +++ /dev/null @@ -1,43 +0,0 @@ -/* Specialized code needed to support construction and destruction of - file-scope objects in C++ and Java code, and to support exception handling. - Copyright (C) 2005 Free Software Foundation, Inc. - Contributed by Analog Devices. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* As a special exception, if you link this library with files - compiled with GCC to produce an executable, this does not cause - the resulting executable to be covered by the GNU General Public License. - This exception does not however invalidate any other reasons why - the executable file might be covered by the GNU General Public License. */ - -/* - * This file supplies function epilogues for the .init and .fini sections. - * It is linked in after all other files. - */ - - .file "crtn.o" - .ident "GNU C crtn.o" - - .section .init - unlink; - rts; - - .section .fini - unlink; - rts; diff --git a/gcc/config/bfin/elf.h b/gcc/config/bfin/elf.h deleted file mode 100644 index 643d5197a67..00000000000 --- a/gcc/config/bfin/elf.h +++ /dev/null @@ -1,16 +0,0 @@ -#define OBJECT_FORMAT_ELF - -#define LOCAL_LABEL_PREFIX "L$" - -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ - sprintf (LABEL, "*%s%s$%d", LOCAL_LABEL_PREFIX, PREFIX, (int) NUM) - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s" - -#undef ENDFILE_SPEC -#define ENDFILE_SPEC "crtend%O%s crtn%O%s" - -#undef USER_LABEL_PREFIX -#define USER_LABEL_PREFIX "_" diff --git a/gcc/config/bfin/lib1funcs.asm b/gcc/config/bfin/lib1funcs.asm deleted file mode 100644 index 778d056fbf4..00000000000 --- a/gcc/config/bfin/lib1funcs.asm +++ /dev/null @@ -1,120 +0,0 @@ -/* libgcc functions for Blackfin. - Copyright (C) 2005 Free Software Foundation, Inc. - Contributed by Analog Devices. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* As a special exception, if you link this library with files - compiled with GCC to produce an executable, this does not cause - the resulting executable to be covered by the GNU General Public License. - This exception does not however invalidate any other reasons why - the executable file might be covered by the GNU General Public License. */ - - -#ifdef L_divsi3 -.text -.align 2 -.global ___divsi3; -.type ___divsi3, STT_FUNC; - -___divsi3: - [--SP]= RETS; - [--SP] = R7; - - R2 = -R0; - CC = R0 < 0; - IF CC R0 = R2; - R7 = CC; - - R2 = -R1; - CC = R1 < 0; - IF CC R1 = R2; - R2 = CC; - R7 = R7 ^ R2; - - CALL ___udivsi3; - - CC = R7; - R1 = -R0; - IF CC R0 = R1; - - R7 = [SP++]; - RETS = [SP++]; - RTS; -#endif - -#ifdef L_modsi3 -.align 2 -.global ___modsi3; -.type ___modsi3, STT_FUNC; - -___modsi3: - [--SP] = RETS; - /* P1 and P2 are preserved by divsi3 and udivsi3. */ - P1 = R0; - P2 = R1; - CALL ___divsi3; - R1 = P1; - R2 = P2; - R2 *= R0; - R0 = R1 - R2; - RETS = [SP++]; - RTS; -#endif - -#ifdef L_udivsi3 -.align 2 -.global ___udivsi3; -.type ___udivsi3, STT_FUNC; - -___udivsi3: - P0 = 32; - LSETUP (0f, 1f) LC0 = P0; - /* upper half of dividend */ - R3 = 0; -0: - /* The first time round in the loop we shift in garbage, but since we - perform 33 shifts, it doesn't matter. */ - R0 = ROT R0 BY 1; - R3 = ROT R3 BY 1; - R2 = R3 - R1; - CC = R3 < R1 (IU); -1: - /* Last instruction of the loop. */ - IF ! CC R3 = R2; - - /* Shift in the last bit. */ - R0 = ROT R0 BY 1; - /* R0 is the result, R3 contains the remainder. */ - R0 = ~ R0; - RTS; -#endif - -#ifdef L_umodsi3 -.align 2 -.global ___umodsi3; -.type ___umodsi3, STT_FUNC; - -___umodsi3: - P1 = RETS; - CALL ___udivsi3; - R0 = R3; - RETS = P1; - RTS; -#endif - diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md deleted file mode 100644 index 53448844dda..00000000000 --- a/gcc/config/bfin/predicates.md +++ /dev/null @@ -1,127 +0,0 @@ -;; Predicate definitions for the Blackfin. -;; -;; This file is part of GCC. -;; -;; GCC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 2, or (at your option) -;; any later version. -;; -;; GCC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. -;; -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. - -;; Return nonzero iff OP is one of the integer constants 1 or 2. -(define_predicate "pos_scale_operand" - (and (match_code "const_int") - (match_test "INTVAL (op) == 1 || INTVAL (op) == 2"))) - -;; Return nonzero iff OP is one of the integer constants 2 or 4. -(define_predicate "scale_by_operand" - (and (match_code "const_int") - (match_test "INTVAL (op) == 2 || INTVAL (op) == 4"))) - -;; Return nonzero if OP is a constant that consists of two parts; lower -;; bits all zero and upper bits all ones. In this case, we can perform -;; an AND operation with a sequence of two shifts. Don't return nonzero -;; if the constant would be cheap to load. -(define_predicate "highbits_operand" - (and (match_code "const_int") - (match_test "log2constp (-INTVAL (op)) && !CONST_7BIT_IMM_P (INTVAL (op))"))) - -;; Return nonzero if OP is suitable as a right-hand side operand for an -;; andsi3 operation. -(define_predicate "rhs_andsi3_operand" - (ior (match_operand 0 "register_operand") - (and (match_code "const_int") - (match_test "log2constp (~INTVAL (op)) || INTVAL (op) == 255 || INTVAL (op) == 65535")))) - -;; Return nonzero if OP is a register or a constant with exactly one bit -;; set. -(define_predicate "regorlog2_operand" - (ior (match_operand 0 "register_operand") - (and (match_code "const_int") - (match_test "log2constp (INTVAL (op))")))) - -;; Like register_operand, but make sure that hard regs have a valid mode. -(define_predicate "valid_reg_operand" - (match_operand 0 "register_operand") -{ - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - if (REGNO (op) < FIRST_PSEUDO_REGISTER) - return HARD_REGNO_MODE_OK (REGNO (op), mode); - return 1; -}) - -;; Return nonzero if OP is the CC register. -(define_predicate "cc_operand" - (and (match_code "reg") - (match_test "REGNO (op) == REG_CC && GET_MODE (op) == BImode"))) - -;; Return nonzero if OP is a register or a 7 bit signed constant. -(define_predicate "reg_or_7bit_operand" - (ior (match_operand 0 "register_operand") - (and (match_code "const_int") - (match_test "CONST_7BIT_IMM_P (INTVAL (op))")))) - -;; Used for secondary reloads, this function returns 1 if OP is of the -;; form (plus (fp) (const_int)). -(define_predicate "fp_plus_const_operand" - (match_code "plus") -{ - rtx op1, op2; - - op1 = XEXP (op, 0); - op2 = XEXP (op, 1); - return (REG_P (op1) - && (REGNO (op1) == FRAME_POINTER_REGNUM - || REGNO (op1) == STACK_POINTER_REGNUM) - && GET_CODE (op2) == CONST_INT); -}) - -;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref, -;; possibly with an offset. -(define_predicate "symbolic_operand" - (ior (match_code "symbol_ref,label_ref") - (and (match_code "const") - (match_test "GET_CODE (XEXP (op,0)) == PLUS - && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF - || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF) - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT")))) - -;; Returns 1 if OP is a plain constant or matched by symbolic_operand. -(define_predicate "symbolic_or_const_operand" - (ior (match_code "const_int,const_double") - (match_operand 0 "symbolic_operand"))) - -;; True for any non-virtual or eliminable register. Used in places where -;; instantiation of such a register may cause the pattern to not be recognized. -(define_predicate "register_no_elim_operand" - (match_operand 0 "register_operand") -{ - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - return !(op == arg_pointer_rtx - || op == frame_pointer_rtx - || (REGNO (op) >= FIRST_PSEUDO_REGISTER - && REGNO (op) <= LAST_VIRTUAL_REGISTER)); -}) - -;; Test for a valid operand for a call instruction. Don't allow the -;; arg pointer register or virtual regs since they may decay into -;; reg + const, which the patterns can't handle. -;; We only allow SYMBOL_REF if !flag_pic. -(define_predicate "call_insn_operand" - (ior (and (match_test "!flag_pic") (match_code "symbol_ref")) - (match_operand 0 "register_no_elim_operand"))) - -;; Test for an operator valid in a conditional branch -(define_predicate "bfin_cbranch_operator" - (match_code "eq,ne")) diff --git a/gcc/config/bfin/t-bfin b/gcc/config/bfin/t-bfin deleted file mode 100644 index 662dc4c3e60..00000000000 --- a/gcc/config/bfin/t-bfin +++ /dev/null @@ -1,29 +0,0 @@ -## Target part of the Makefile - -LIB1ASMSRC = bfin/lib1funcs.asm -LIB1ASMFUNCS = _divsi3 _udivsi3 _umodsi3 _modsi3 - -EXTRA_PARTS = crtbegin.o crtend.o crti.o crtn.o - -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - cat $(srcdir)/config/fp-bit.c > dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -# This shouldn't be needed here. I added it to the specs file for now, until -# it is fixed in binutils (if it is necessary). -GCC_CFLAGS += -N - -# Assemble startup files. -$(T)crti.o: $(srcdir)/config/bfin/crti.s $(GCC_PASSES) - $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ - -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/bfin/crti.s - -$(T)crtn.o: $(srcdir)/config/bfin/crtn.s $(GCC_PASSES) - $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ - -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/bfin/crtn.s diff --git a/gcc/config/bfin/t-bfin-elf b/gcc/config/bfin/t-bfin-elf deleted file mode 100644 index 662dc4c3e60..00000000000 --- a/gcc/config/bfin/t-bfin-elf +++ /dev/null @@ -1,29 +0,0 @@ -## Target part of the Makefile - -LIB1ASMSRC = bfin/lib1funcs.asm -LIB1ASMFUNCS = _divsi3 _udivsi3 _umodsi3 _modsi3 - -EXTRA_PARTS = crtbegin.o crtend.o crti.o crtn.o - -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - cat $(srcdir)/config/fp-bit.c > dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -# This shouldn't be needed here. I added it to the specs file for now, until -# it is fixed in binutils (if it is necessary). -GCC_CFLAGS += -N - -# Assemble startup files. -$(T)crti.o: $(srcdir)/config/bfin/crti.s $(GCC_PASSES) - $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ - -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/bfin/crti.s - -$(T)crtn.o: $(srcdir)/config/bfin/crtn.s $(GCC_PASSES) - $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ - -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/bfin/crtn.s diff --git a/gcc/testsuite/g++.dg/abi/covariant5.C b/gcc/testsuite/g++.dg/abi/covariant5.C deleted file mode 100644 index 03e55583d03..00000000000 --- a/gcc/testsuite/g++.dg/abi/covariant5.C +++ /dev/null @@ -1,52 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation, Inc. -// Contributed by Nathan Sidwell 4 Apr 2005 <nathan@codesourcery.com> - -// { dg-do run } - -// PR 20746: Covariant return pointer could be null. - -// Origin: yanliu@ca.ibm.com -// nathan@codesourcery.com - -struct A { - virtual void One (); -}; -struct B { - virtual B *Two (); - virtual B &Three (); -}; - -struct C : A, B -{ - virtual C *Two (); - virtual C &Three (); -}; -void A::One () {} -B *B::Two() {return this;} -B &B::Three() {return *this;} -C *C::Two () {return 0;} -C &C::Three () {return *(C *)0;} - -B *Foo (B *b) -{ - return b->Two (); -} - -B &Bar (B *b) -{ - return b->Three (); -} - -int main () -{ - C c; - - /* We should not adjust a null pointer. */ - if (Foo (&c)) - return 1; - /* But we should adjust a (bogus) null reference. */ - if (!&Bar (&c)) - return 2; - - return 0; -} diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class1.C b/gcc/testsuite/g++.dg/lookup/hidden-class1.C deleted file mode 100644 index fc71e96fb7f..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class1.C +++ /dev/null @@ -1,8 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; - B *b; // { dg-error "no type|expected" } -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class2.C b/gcc/testsuite/g++.dg/lookup/hidden-class2.C deleted file mode 100644 index 19287a5fb21..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class2.C +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; -}; - -class B* b; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class3.C b/gcc/testsuite/g++.dg/lookup/hidden-class3.C deleted file mode 100644 index 50a7e331cbb..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class3.C +++ /dev/null @@ -1,10 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; - - class B; - B *b; -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class4.C b/gcc/testsuite/g++.dg/lookup/hidden-class4.C deleted file mode 100644 index c407692caf9..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class4.C +++ /dev/null @@ -1,10 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; -}; - -class B *b; -B *c; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class5.C b/gcc/testsuite/g++.dg/lookup/hidden-class5.C deleted file mode 100644 index 1cf06bcc395..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class5.C +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; -}; - -B* b; // { dg-error "expected" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class6.C b/gcc/testsuite/g++.dg/lookup/hidden-class6.C deleted file mode 100644 index 96425353911..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class6.C +++ /dev/null @@ -1,14 +0,0 @@ -// { dg-do compile } - -// Origin: Jay Cox <jaycox@gimp.org> - -// PR c++/1016: Name lookup for injected friend class - -class B; - -namespace N { - class A { - friend class B; - B* b; - }; -} diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class7.C b/gcc/testsuite/g++.dg/lookup/hidden-class7.C deleted file mode 100644 index f681cd649f1..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class7.C +++ /dev/null @@ -1,13 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; -}; - -class C { - friend class B; -}; - -B *b; // { dg-error "expected" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class8.C b/gcc/testsuite/g++.dg/lookup/hidden-class8.C deleted file mode 100644 index ea4e2f1bbdc..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class8.C +++ /dev/null @@ -1,12 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -namespace N { - class A { - friend class B; - }; -} - -class N::B { // { dg-error "not name a class" } -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-class9.C b/gcc/testsuite/g++.dg/lookup/hidden-class9.C deleted file mode 100644 index de86b12694e..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-class9.C +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -namespace N { - class A { - friend class B; - }; -} - -using N::B; // { dg-error "declared" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class1.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class1.C deleted file mode 100644 index c92b7f66a1a..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class1.C +++ /dev/null @@ -1,8 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; - B<int> *b; // { dg-error "no type|expected" } -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class10.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class10.C deleted file mode 100644 index 2134635a263..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class10.C +++ /dev/null @@ -1,12 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -namespace N { - class A { - template <class T> friend class B; - }; -} - -template <class T> class N::B { // { dg-error "not name a class" } -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class11.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class11.C deleted file mode 100644 index 6e8cbdbb654..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class11.C +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -namespace N { - class A { - template <class T> friend class B; - }; -} - -using N::B; // { dg-error "declared" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class2.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class2.C deleted file mode 100644 index 56ba76b3aed..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class2.C +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; -}; - -class B* b; // { dg-error "argument required|invalid" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class3.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class3.C deleted file mode 100644 index 3f96622ea4a..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class3.C +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; - template <class T> class B; - B<int> *b; -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class4.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class4.C deleted file mode 100644 index 02dc9c3e50f..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class4.C +++ /dev/null @@ -1,9 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; -}; - -B<int> *b; // { dg-error "expected" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class5.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class5.C deleted file mode 100644 index e6b30b291f9..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class5.C +++ /dev/null @@ -1,10 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; -}; - -template <class T> class B; -B<int>* b; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class6.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class6.C deleted file mode 100644 index 2072695ba7d..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class6.C +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class B; -namespace N { - class A { - template <class T> friend class B; - B* b; - }; -} diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class7.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class7.C deleted file mode 100644 index 22804d782a0..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class7.C +++ /dev/null @@ -1,13 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; -}; - -class C { - template <class T> friend class B; -}; - -B<int> *b; // { dg-error "expected" } diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class8.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class8.C deleted file mode 100644 index 247c78cf37a..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class8.C +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - template <class T> friend class B; -}; - -class C { - friend class B; // { dg-error "argument required|friend" } -}; diff --git a/gcc/testsuite/g++.dg/lookup/hidden-temp-class9.C b/gcc/testsuite/g++.dg/lookup/hidden-temp-class9.C deleted file mode 100644 index 783139b66ab..00000000000 --- a/gcc/testsuite/g++.dg/lookup/hidden-temp-class9.C +++ /dev/null @@ -1,11 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation -// Contributed by Kriang Lerdsuwanakij <lerdsuwa@users.sourceforge.net> -// { dg-do compile } - -class A { - friend class B; -}; - -class C { - template <class T> friend class B; // { dg-error "not a template" } -}; diff --git a/gcc/testsuite/g++.dg/template/spec20.C b/gcc/testsuite/g++.dg/template/spec20.C deleted file mode 100644 index 71548e4af9b..00000000000 --- a/gcc/testsuite/g++.dg/template/spec20.C +++ /dev/null @@ -1,19 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation, Inc. -// Contributed by Nathan Sidwell 31 Mar 2005 <nathan@codesourcery.com> - -// Origin: Giovanni Bajo <giovannibajo@libero.it> -// Bug 19203: Failure to implement DR 214 - -template <class A> -void foo(const A& a); - -template <class RET, class ARG1> -int foo(RET (&)(ARG1)); // this one - - -float decl(int); - -int bar(void) -{ - return foo(decl); -} diff --git a/gcc/testsuite/g++.dg/template/spec21.C b/gcc/testsuite/g++.dg/template/spec21.C deleted file mode 100644 index e04ac5a2da9..00000000000 --- a/gcc/testsuite/g++.dg/template/spec21.C +++ /dev/null @@ -1,28 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation, Inc. -// Contributed by Nathan Sidwell 31 Mar 2005 <nathan@codesourcery.com> - -// { dg-do run } -// DR214 - -template <class T> T f(int) {return 0;} -template <class T, class U> T f(U){return 1;} - -template <typename T, typename R> T checked_cast (R const &) {return 0;} -template <typename T, typename R> T checked_cast (R *) {return 1;} - - -int main () -{ - int i = 0; - - if (f<int>(1)) - return 1; - - if (checked_cast<int>(i) != 0) - return 2; - - if (checked_cast<int>(&i) != 1) - return 3; - - return 0; -} diff --git a/gcc/testsuite/g++.dg/template/spec22.C b/gcc/testsuite/g++.dg/template/spec22.C deleted file mode 100644 index e2d439c9252..00000000000 --- a/gcc/testsuite/g++.dg/template/spec22.C +++ /dev/null @@ -1,22 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation, Inc. -// Contributed by Nathan Sidwell 2 Apr 2005 <nathan@codesourcery.com> - -// PR 20723 -// Origin: Andrew Pinski <pinskia@gcc.gnu.org> -// Nathan Sidwell <nathan@gcc.gnu.org> - -template <typename T> -int operator+ (T const &, int); // { dg-error "T = Foo" "" } - -struct Foo -{ - template <typename T> - int operator+ (T) const; // { dg-error "T = int" "" } -}; - -int main () -{ - Foo f; - - return f + 0; // { dg-error "ambiguous overload" "" } -} diff --git a/gcc/testsuite/g++.dg/template/spec23.C b/gcc/testsuite/g++.dg/template/spec23.C deleted file mode 100644 index 00272ad4995..00000000000 --- a/gcc/testsuite/g++.dg/template/spec23.C +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright (C) 2005 Free Software Foundation, Inc. -// Contributed by Nathan Sidwell 2 Apr 2005 <nathan@codesourcery.com> - -// PR 20723 -// Origin: Andrew Pinski <pinskia@gcc.gnu.org> -// Nathan Sidwell <nathan@gcc.gnu.org> - -struct Foo -{ - template <typename T> - Foo (const T &); // { dg-error "T = Bar" "" } -}; - -struct Bar -{ - template <typename T> - operator T () const; // { dg-error "T = Foo" "" } -}; - -Foo Quux (Bar const &b) -{ - return b; // { dg-error "ambiguous" "" } -} - - diff --git a/gcc/testsuite/gfortran.dg/comma_format_extension_1.f b/gcc/testsuite/gfortran.dg/comma_format_extension_1.f deleted file mode 100644 index a3a5a98f155..00000000000 --- a/gcc/testsuite/gfortran.dg/comma_format_extension_1.f +++ /dev/null @@ -1,11 +0,0 @@ -! { dg-do compile } -! { dg-options "" } -! test that the extension for a missing comma is accepted - - subroutine mysub - dimension ibar(5) - write (3,1001) ( ibar(m), m = 1, 5 ) - - 1001 format (/5x,' ',i4' '/ ) - return - end diff --git a/gcc/testsuite/gfortran.dg/comma_format_extension_2.f b/gcc/testsuite/gfortran.dg/comma_format_extension_2.f deleted file mode 100644 index 7eb17b58434..00000000000 --- a/gcc/testsuite/gfortran.dg/comma_format_extension_2.f +++ /dev/null @@ -1,10 +0,0 @@ -! { dg-do compile } -! test that the extension for a missing comma is accepted - - subroutine mysub - dimension ibar(5) - write (3,1001) ( ibar(m), m = 1, 5 ) - - 1001 format (/5x,' ',i4' '/ ) ! { dg-warning "Missing comma" } - return - end diff --git a/gcc/testsuite/gfortran.dg/comma_format_extension_3.f b/gcc/testsuite/gfortran.dg/comma_format_extension_3.f deleted file mode 100644 index 15ee18905c4..00000000000 --- a/gcc/testsuite/gfortran.dg/comma_format_extension_3.f +++ /dev/null @@ -1,16 +0,0 @@ -! PR libfortran/15332 and PR fortran/13257 -! We used to accept this as an extension but -! did do the correct thing at runtime. -! Note the missing , before i1 in the format. -! { do-do run } -! { dg-options "" } - character*12 c - - write (c,100) 0, 1 - if (c .ne. 'i = 0, j = 1') call abort - - write (c,100) 0 - if (c .ne. 'i = 0 ') call abort - - 100 format ('i = 'i1,:,', j = ',i1) - end diff --git a/gcc/testsuite/gfortran.dg/comma_format_extension_4.f b/gcc/testsuite/gfortran.dg/comma_format_extension_4.f deleted file mode 100644 index 5f6ecc5073b..00000000000 --- a/gcc/testsuite/gfortran.dg/comma_format_extension_4.f +++ /dev/null @@ -1,10 +0,0 @@ -! PR fortran/13257 -! Note the missing , before i1 in the format. -! { do-do run } -! { dg-options "" } - character*5 c - write (c,1001) 1 - if (c .ne. ' 1 ') call abort - - 1001 format (' ',i4' ') - end diff --git a/gcc/testsuite/gfortran.dg/eor_handling_1.f90 b/gcc/testsuite/gfortran.dg/eor_handling_1.f90 deleted file mode 100644 index 241f8a0fe4e..00000000000 --- a/gcc/testsuite/gfortran.dg/eor_handling_1.f90 +++ /dev/null @@ -1,14 +0,0 @@ -! { dg-do run } -! PR 17992: Reading an empty file should yield zero with pad='YES' -! (which is the default). -! Test case supplied by milan@cmm.ki.si. -program main - open(77,status='scratch') - write(77,'(A)') '','' - rewind(77) - i = 42 - j = 42 - read(77,'(/2i2)') i,j - if (i /= 0 .or. j /= 0) call abort - close(77) -end program main diff --git a/gcc/testsuite/gfortran.dg/eor_handling_2.f90 b/gcc/testsuite/gfortran.dg/eor_handling_2.f90 deleted file mode 100644 index 5eb62f8a894..00000000000 --- a/gcc/testsuite/gfortran.dg/eor_handling_2.f90 +++ /dev/null @@ -1,13 +0,0 @@ -! { dg-do run } -! PR 19568: Don't read across end of line when the format is longer -! than the line length and pad='yes' (default) -program main - character(len=1) c1(10),c2(10) - open(77,status='scratch') - write(77,'(A)') 'Line 1','Line 2','Line 3' - rewind(77) - read(77,'(10A1)'), c1 - read(77,'(10A1)'), c2 - if (c1(1) /= 'L' .or. c2(1) /= 'L') call abort - close(77) -end program main diff --git a/gcc/testsuite/gfortran.dg/eor_handling_3.f90 b/gcc/testsuite/gfortran.dg/eor_handling_3.f90 deleted file mode 100644 index 4225e867a85..00000000000 --- a/gcc/testsuite/gfortran.dg/eor_handling_3.f90 +++ /dev/null @@ -1,13 +0,0 @@ -! { dg-do run } -! PR 19595: Handle end-of-record condition with pad=yes (default) -program main - integer i1, i2 - open(77,status='scratch') - write (77,'(A)') '123','456' - rewind(77) - read(77,'(2I2)',advance='no',eor=100) i1,i2 - call abort -100 continue - if (i1 /= 12 .or. i2 /= 3) call abort - close(77) -end program main diff --git a/gcc/testsuite/gfortran.dg/eor_handling_4.f90 b/gcc/testsuite/gfortran.dg/eor_handling_4.f90 deleted file mode 100644 index 300c10b820a..00000000000 --- a/gcc/testsuite/gfortran.dg/eor_handling_4.f90 +++ /dev/null @@ -1,17 +0,0 @@ -! { dg-do run } -! PR 20092, 20131: Handle end-of-record condition with pad=yes (default) -! for standard input. This test case only really tests anything if, -! by changing unit 5, you get to manipulate the standard input. -program main - character(len=1) a(80) - close(5) - open(5,status="scratch") - write(5,'(A)') 'one', 'two', 's' - rewind(5) - do i=1,4 - read(5,'(80a1)') a - if (a(1) == 's') goto 100 - end do - call abort -100 continue -end program main diff --git a/gcc/testsuite/gfortran.dg/eor_handling_5.f90 b/gcc/testsuite/gfortran.dg/eor_handling_5.f90 deleted file mode 100644 index c116fb7bdea..00000000000 --- a/gcc/testsuite/gfortran.dg/eor_handling_5.f90 +++ /dev/null @@ -1,19 +0,0 @@ -! { dg-do run } -! PR 20661: Handle non-advancing I/O with iostat -! Test case by Walt Brainerd, The Fortran Company - -program fc002 - character(len=1) :: c - integer :: k,k2 - character(len=*), parameter :: f="(a)" - open(11,status="scratch", iostat=k) - if (k /= 0) call abort - write(11,f) "x" - rewind (11) - read(11, f, advance="no", iostat=k) c - if (k /= 0) call abort - read(11, f, advance="no", iostat=k) c - if (k >= 0) call abort - read(11, f, advance="no", iostat=k2) c - if (k2 >= 0 .or. k == k2) call abort -end program fc002 diff --git a/gcc/testsuite/gfortran.dg/noadv_size.f90 b/gcc/testsuite/gfortran.dg/noadv_size.f90 deleted file mode 100644 index a3a88b18ca7..00000000000 --- a/gcc/testsuite/gfortran.dg/noadv_size.f90 +++ /dev/null @@ -1,11 +0,0 @@ -! { dg-do run } -! PR 20774: Handle size parameter for non-advancing I/O correctly -program main - open(77,status='scratch') - write(77,'(A)') '123' - rewind(77) - read(77,'(2I2)',advance='no',iostat=k,size=n) i1,i2 - if (k >=0) call abort - if (n /= 3) call abort - if (i1 /= 12 .or. i2 /= 3) call abort -end program main diff --git a/gcc/testsuite/gfortran.dg/pad_no.f90 b/gcc/testsuite/gfortran.dg/pad_no.f90 deleted file mode 100644 index c023adec815..00000000000 --- a/gcc/testsuite/gfortran.dg/pad_no.f90 +++ /dev/null @@ -1,15 +0,0 @@ -! { dg-do run } -! Test correct operation for pad='no'. -program main - character(len=1) line(2) - line = 'x' - open(77,status='scratch',pad='no') - write(77,'(A)') 'a','b' - rewind(77) - read(77,'(2A)',iostat=i) line(1) - if (line(1) /= 'a' .or. line(2) /= 'x') call abort - rewind(77) - line = 'y' - read(77,'(2A)',iostat=i,advance='no') line - if (line(1) /= 'a' .or. line(2) /= 'y') call abort -end program main diff --git a/libiberty/fopen_unlocked.c b/libiberty/fopen_unlocked.c deleted file mode 100644 index 8f9f300d101..00000000000 --- a/libiberty/fopen_unlocked.c +++ /dev/null @@ -1,110 +0,0 @@ -/* Implement fopen_unlocked and related functions. - Copyright (C) 2005 Free Software Foundation, Inc. - Written by Kaveh R. Ghazi <ghazi@caip.rutgers.edu>. - -This file is part of the libiberty library. -Libiberty is free software; you can redistribute it and/or -modify it under the terms of the GNU Library General Public -License as published by the Free Software Foundation; either -version 2 of the License, or (at your option) any later version. - -Libiberty is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -Library General Public License for more details. - -You should have received a copy of the GNU Library General Public -License along with libiberty; see the file COPYING.LIB. If -not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* - -@deftypefn Extension void unlock_stream (FILE * @var{stream}) - -If the OS supports it, ensure that the supplied stream is setup to -avoid any multi-threaded locking. Otherwise leave the @code{FILE} -pointer unchanged. If the @var{stream} is @code{NULL} do nothing. - -@end deftypefn - -@deftypefn Extension FILE * fopen_unlocked (const char *@var{path}, const char * @var{mode}) - -Opens and returns a @code{FILE} pointer via @code{fopen}. If the -operating system supports it, ensure that the stream is setup to avoid -any multi-threaded locking. Otherwise return the @code{FILE} pointer -unchanged. - -@end deftypefn - -@deftypefn Extension FILE * fdopen_unlocked (int @var{fildes}, const char * @var{mode}) - -Opens and returns a @code{FILE} pointer via @code{fdopen}. If the -operating system supports it, ensure that the stream is setup to avoid -any multi-threaded locking. Otherwise return the @code{FILE} pointer -unchanged. - -@end deftypefn - -@deftypefn Extension FILE * freopen_unlocked (const char * @var{path}, const char * @var{mode}, FILE * @var{stream}) - -Opens and returns a @code{FILE} pointer via @code{freopen}. If the -operating system supports it, ensure that the stream is setup to avoid -any multi-threaded locking. Otherwise return the @code{FILE} pointer -unchanged. - -@end deftypefn - -*/ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif -#include <stdio.h> -#ifdef HAVE_STDIO_EXT_H -#include <stdio_ext.h> -#endif - -#include "libiberty.h" - -/* This is an inline helper function to consolidate attempts to unlock - a stream. */ - -static inline void -unlock_1 (FILE *const fp ATTRIBUTE_UNUSED) -{ -#if defined(HAVE___FSETLOCKING) && defined(FSETLOCKING_BYCALLER) - if (fp) - __fsetlocking (fp, FSETLOCKING_BYCALLER); -#endif -} - -void -unlock_stream(FILE *fp) -{ - unlock_1 (fp); -} - -FILE * -fopen_unlocked (const char *path, const char *mode) -{ - FILE *const fp = fopen (path, mode); - unlock_1 (fp); - return fp; -} - -FILE * -fdopen_unlocked (int fildes, const char *mode) -{ - FILE *const fp = fdopen (fildes, mode); - unlock_1 (fp); - return fp; -} - -FILE * -freopen_unlocked (const char *path, const char *mode, FILE *stream) -{ - FILE *const fp = freopen (path, mode, stream); - unlock_1 (fp); - return fp; -} diff --git a/libstdc++-v3/testsuite/libstdc++-abi/abi.exp b/libstdc++-v3/testsuite/libstdc++-abi/abi.exp deleted file mode 100644 index f226e0aaf77..00000000000 --- a/libstdc++-v3/testsuite/libstdc++-abi/abi.exp +++ /dev/null @@ -1,43 +0,0 @@ -# Copyright (C) 2005 Free Software Foundation, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -# If there is no baseline file, or we can't find the library, skip -# this test. -if { ![info exists baseline_file] \ - || ![file exists $baseline_file] \ - || ![file exists "../src/.libs/libstdc++.so"] } { - return -} - -# Figure out what symbols are defined by the active build of the library. -remote_exec "build" "$srcdir/../scripts/extract_symvers" \ - [list "../src/.libs/libstdc++.so" "current_symbols.txt"] - -# Build the support objects. -v3-build_support - -# Build the abi_check program. -if { [v3_target_compile "$srcdir/testsuite_abi_check.cc" "abi_check" \ - "executable" [list "additional_flags=-w"]] != "" } { - error "could not compile testsuite_abi_check.cc" -} - -remote_download "target" $baseline_file "baseline_symbols.txt" -remote_download "target" "current_symbols.txt" "current_symbols.txt" -set result [${tool}_load "./abi_check" \ - [list "--check-verbose" "current_symbols.txt" \ - "baseline_symbols.txt"]] -[lindex $result 0] "abi_check" diff --git a/libstdc++-v3/testsuite/testsuite_abi_check.cc b/libstdc++-v3/testsuite/testsuite_abi_check.cc deleted file mode 100644 index 028db89c93e..00000000000 --- a/libstdc++-v3/testsuite/testsuite_abi_check.cc +++ /dev/null @@ -1,95 +0,0 @@ -// -*- C++ -*- - -// Copyright (C) 2004 Free Software Foundation, Inc. - -// This library is free software; you can redistribute it and/or -// modify it under the terms of the GNU General Public License as -// published by the Free Software Foundation; either version 2, or (at -// your option) any later version. - -// This library is distributed in the hope that it will be useful, but -// WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -// General Public License for more details. - -// You should have received a copy of the GNU General Public License -// along with this library; see the file COPYING. If not, write to -// the Free Software Foundation, 59 Temple Place - Suite 330, Boston, -// MA 02111-1307, USA. - -// As a special exception, you may use this file as part of a free -// software library without restriction. Specifically, if other files -// instantiate templates or use macros or inline functions from this -// file, or you compile this file and link it with other files to -// produce an executable, this file does not by itself cause the -// resulting executable to be covered by the GNU General Public -// License. This exception does not however invalidate any other -// reasons why the executable file might be covered by the GNU General -// Public License. - -// Benjamin Kosnik <bkoz@redhat.com> -// Blame subsequent hacks on Loren J. Rittle <ljrittle@acm.org>, Phil -// Edwards <pme@gcc.gnu.org>, and a cast of dozens at libstdc++@gcc.gnu.org. - -#include "testsuite_abi.h" -#include <iostream> -#include <unistd.h> // for access(2) - -int -main(int argc, char** argv) -{ - using namespace std; - - // Get arguments. (Heading towards getopt_long, I can feel it.) - string argv1 = argc > 1 ? argv[1] : ""; - if (argv1 == "--help" || argc < 4) - { - cerr << "usage: abi_check --check current baseline\n" - " --check-verbose current baseline\n" - " --examine symbol current\n" - " --help\n" - "\n" - "All arguments are string literals.\n" - "CURRENT is a file generated byextract_symvers.\n" - "BASELINE is a file from config/abi.\n" - "SYMBOL is a mangled name.\n" - << endl; - exit(1); - } - - if (argv1.find("--check") != string::npos) - { - bool verbose = false; - if (argv1 == "--check-verbose") - verbose = true; - - // Quick sanity/setup check for arguments. - const char* test_file = argv[2]; - const char* baseline_file = argv[3]; - if (access(test_file, R_OK) != 0) - { - cerr << "Cannot read symbols file " << test_file - << ", did you forget to build first?" << endl; - exit(1); - } - if (access(baseline_file, R_OK) != 0) - { - cerr << "Cannot read baseline file " << baseline_file << endl; - exit(1); - } - if (!compare_symbols(baseline_file, test_file, verbose)) - exit (1); - } - - if (argv1 == "--examine") - { - const char* file = argv[3]; - if (access(file, R_OK) != 0) - { - cerr << "Cannot read symbol file " << file << endl; - exit(1); - } - examine_symbol(argv[2], file); - } - return 0; -} |