diff options
| author | yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-06-12 12:55:11 +0000 |
|---|---|---|
| committer | yroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-06-12 12:55:11 +0000 |
| commit | 81ce9ac16dee572617df05c9fc8c7aa6f3cf7996 (patch) | |
| tree | 4624b758f2dab1c6bc7fddfdafb27a810bcef7b2 | |
| parent | 671db3388b8d2ce0a83f88901d3b3033d5a437e4 (diff) | |
2014-06-04 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211211.
2014-06-04 Bin Cheng <bin.cheng@arm.com>
* config/aarch64/aarch64.c (aarch64_classify_address)
(aarch64_legitimize_reload_address): Support full addressing modes
for vector modes.
* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211584 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog.linaro | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 16 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 10 |
3 files changed, 24 insertions, 13 deletions
diff --git a/gcc/ChangeLog.linaro b/gcc/ChangeLog.linaro index b0b429b7766..eb0dac7657c 100644 --- a/gcc/ChangeLog.linaro +++ b/gcc/ChangeLog.linaro @@ -1,3 +1,14 @@ +2014-06-04 Yvan Roux <yvan.roux@linaro.org> + + Backport from trunk r211211. + 2014-06-04 Bin Cheng <bin.cheng@arm.com> + + * config/aarch64/aarch64.c (aarch64_classify_address) + (aarch64_legitimize_reload_address): Support full addressing modes + for vector modes. + * config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>) + (*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates. + 2014-05-25 Yvan Roux <yvan.roux@linaro.org> Backport from trunk r209906. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 108bc8d8893..e84de9dcbe0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -19,8 +19,8 @@ ;; <http://www.gnu.org/licenses/>. (define_expand "mov<mode>" - [(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "") - (match_operand:VALL 1 "aarch64_simd_general_operand" ""))] + [(set (match_operand:VALL 0 "nonimmediate_operand" "") + (match_operand:VALL 1 "general_operand" ""))] "TARGET_SIMD" " if (GET_CODE (operands[0]) == MEM) @@ -29,8 +29,8 @@ ) (define_expand "movmisalign<mode>" - [(set (match_operand:VALL 0 "aarch64_simd_nonimmediate_operand" "") - (match_operand:VALL 1 "aarch64_simd_general_operand" ""))] + [(set (match_operand:VALL 0 "nonimmediate_operand" "") + (match_operand:VALL 1 "general_operand" ""))] "TARGET_SIMD" { /* This pattern is not permitted to fail during expansion: if both arguments @@ -91,9 +91,9 @@ ) (define_insn "*aarch64_simd_mov<mode>" - [(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand" + [(set (match_operand:VD 0 "nonimmediate_operand" "=w, m, w, ?r, ?w, ?r, w") - (match_operand:VD 1 "aarch64_simd_general_operand" + (match_operand:VD 1 "general_operand" "m, w, w, w, r, r, Dn"))] "TARGET_SIMD && (register_operand (operands[0], <MODE>mode) @@ -119,9 +119,9 @@ ) (define_insn "*aarch64_simd_mov<mode>" - [(set (match_operand:VQ 0 "aarch64_simd_nonimmediate_operand" + [(set (match_operand:VQ 0 "nonimmediate_operand" "=w, m, w, ?r, ?w, ?r, w") - (match_operand:VQ 1 "aarch64_simd_general_operand" + (match_operand:VQ 1 "general_operand" "m, w, w, w, r, r, Dn"))] "TARGET_SIMD && (register_operand (operands[0], <MODE>mode) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 94e05bb5e3f..2d8e93df2e5 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3075,11 +3075,11 @@ aarch64_classify_address (struct aarch64_address_info *info, enum rtx_code code = GET_CODE (x); rtx op0, op1; bool allow_reg_index_p = - outer_code != PARALLEL && GET_MODE_SIZE(mode) != 16; - + outer_code != PARALLEL && (GET_MODE_SIZE (mode) != 16 + || aarch64_vector_mode_supported_p (mode)); /* Don't support anything other than POST_INC or REG addressing for AdvSIMD. */ - if (aarch64_vector_mode_p (mode) + if (aarch64_vect_struct_mode_p (mode) && (code != POST_INC && code != REG)) return false; @@ -4009,8 +4009,8 @@ aarch64_legitimize_reload_address (rtx *x_p, { rtx x = *x_p; - /* Do not allow mem (plus (reg, const)) if vector mode. */ - if (aarch64_vector_mode_p (mode) + /* Do not allow mem (plus (reg, const)) if vector struct mode. */ + if (aarch64_vect_struct_mode_p (mode) && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1))) |