RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.cc (register_frm): New function.
	(DEF_RVV_FRM_ENUM): New macro.
	(handle_pragma_vector): Add FRM enum
	* config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
	(RNE): Ditto.
	(RTZ): Ditto.
	(RDN): Ditto.
	(RUP): Ditto.
	(RMM): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/frm-1.c: New test.

3 files changed, 61 insertions, 0 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index f69f6c49c7e..9fea70709fd 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4031,6 +4031,19 @@ register_vxrm ()
   lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values);
 }
 
+/* Register the frm enum.  */
+static void
+register_frm ()
+{
+  auto_vec<string_int_pair, 5> values;
+#define DEF_RVV_FRM_ENUM(NAME, VALUE)                                          \
+  values.quick_push (string_int_pair ("FRM_" #NAME, VALUE));
+#include "riscv-vector-builtins.def"
+#undef DEF_RVV_FRM_ENUM
+
+  lang_hooks.types.simulate_enum_decl (input_location, "RVV_FRM", &values);
+}
+
 /* Implement #pragma riscv intrinsic vector.  */
 void
 handle_pragma_vector ()
@@ -4048,6 +4061,7 @@ handle_pragma_vector ()
 
   /* Define the enums.  */
   register_vxrm ();
+  register_frm ();
 
   /* Define the functions.  */
   function_table = new hash_table<registered_function_hasher> (1023);
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 533853e09b1..61346e53d7b 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -94,6 +94,11 @@ along with GCC; see the file COPYING3.  If not see
 #define DEF_RVV_VXRM_ENUM(NAME, VALUE)
 #endif
 
+/* Define RVV_FRM rounding mode enum for floating-point intrinsics.  */
+#ifndef DEF_RVV_FRM_ENUM
+#define DEF_RVV_FRM_ENUM(NAME, VALUE)
+#endif
+
 /* SEW/LMUL = 64:
    Only enable when TARGET_MIN_VLEN > 32.
    Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128.
@@ -674,6 +679,12 @@ DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)
 DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN)
 DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
 
+DEF_RVV_FRM_ENUM (RNE, FRM_RNE)
+DEF_RVV_FRM_ENUM (RTZ, FRM_RTZ)
+DEF_RVV_FRM_ENUM (RDN, FRM_RDN)
+DEF_RVV_FRM_ENUM (RUP, FRM_RUP)
+DEF_RVV_FRM_ENUM (RMM, FRM_RMM)
+
 #include "riscv-vector-type-indexer.gen.def"
 
 #undef DEF_RVV_PRED_TYPE
@@ -683,3 +694,4 @@ DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD)
 #undef DEF_RVV_BASE_TYPE
 #undef DEF_RVV_TYPE_INDEX
 #undef DEF_RVV_VXRM_ENUM
+#undef DEF_RVV_FRM_ENUM
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
new file mode 100644
index 00000000000..f5635fb959e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t f0 ()
+{
+  return FRM_RNE;
+}
+
+size_t f1 ()
+{
+  return FRM_RTZ;
+}
+
+size_t f2 ()
+{
+  return FRM_RDN;
+}
+
+size_t f3 ()
+{
+  return FRM_RUP;
+}
+
+size_t f4 ()
+{
+  return FRM_RMM;
+}
+
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*4} 1} } */