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| author | Michael Collison <michael.collison@linaro.org> | 2015-06-24 23:58:44 -0700 |
|---|---|---|
| committer | Michael Collison <michael.collison@linaro.org> | 2015-06-25 00:27:23 -0700 |
| commit | 6c9180df69ea04b73c15dbc706da75eba8845880 (patch) | |
| tree | be20d15564258572547cdd8542380b826e2555d4 | |
| parent | b9ea6dbbecce6a4c7772efee97d9241858ff1f8d (diff) | |
Detect smin/umin idiom from TCWG-146linaro-local/tcwg-146
Change-Id: I8622e3ccb566db46acbce2879a357fdd1fca91a6
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 38 |
2 files changed, 45 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 550f7888b2a..49d8b6e2227 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-06-24 Michael Collison <michael.collison@linaro.org + + 2012-05-01 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> + + * gcc/config/arm/arm.md (*arm_smin_cmp): New pattern. + (*arm_umin_cmp): Likewise. + 2015-06-24 Kaz Kojima <kkojima@gcc.gnu.org> PR target/66563 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1ac8af099ce..994c95f0e24 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3455,6 +3455,28 @@ (set_attr "type" "multiple,multiple")] ) +;; t = (s/u)min (x, y) +;; cc = cmp (t, z) +;; is the same as +;; cmp x, z +;; cmpge(u) y, z + +(define_insn_and_split "*arm_smin_cmp" + [(set (reg:CC CC_REGNUM) + (compare:CC + (smin:SI (match_operand:SI 0 "s_register_operand" "r") + (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_32BIT" + "#" + "" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 0) (match_dup 2))) + (cond_exec (ge:CC (reg:CC CC_REGNUM) (const_int 0)) + (set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))))] +) + (define_expand "umaxsi3" [(parallel [ (set (match_operand:SI 0 "s_register_operand" "") @@ -3521,6 +3543,22 @@ (set_attr "type" "store1")] ) +(define_insn_and_split "*arm_umin_cmp" + [(set (reg:CC CC_REGNUM) + (compare:CC + (umin:SI (match_operand:SI 0 "s_register_operand" "r") + (match_operand:SI 1 "s_register_operand" "r")) + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_32BIT" + "#" + "" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 0) (match_dup 2))) + (cond_exec (geu:CC (reg:CC CC_REGNUM) (const_int 0)) + (set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))))] +) + (define_insn "*store_minmaxsi" [(set (match_operand:SI 0 "memory_operand" "=m") (match_operator:SI 3 "minmax_operator" |