diff options
author | Yvan Roux <yvan.roux@linaro.org> | 2017-07-05 09:20:09 +0200 |
---|---|---|
committer | Yvan Roux <yvan.roux@linaro.org> | 2017-07-05 14:30:01 +0000 |
commit | b1241da7bee4160581e6dec94b88e5d4eb15ec56 (patch) | |
tree | 62f812e95f900f73eb118de3f64b118de29891f5 | |
parent | ed3800bb37f706a0d308230e100106ae50c2bad9 (diff) |
gcc/
Backport from trunk r249187.
2017-06-14 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@cavium.com>
PR target/71663
* config/aarch64/aarch64.c (aarch64_expand_vector_init):
Improve vector initialization code gen for only variable case.
gcc/testsuite/
Backport from trunk r249187.
2017-06-14 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@cavium.com>
PR target/71663
* gcc.target/aarch64/vect-init-1.c: Newtestcase.
* gcc.target/aarch64/vect-init-2.c: Likewise.
* gcc.target/aarch64/vect-init-3.c: Likewise.
* gcc.target/aarch64/vect-init-4.c: Likewise.
* gcc.target/aarch64/vect-init-5.c: Likewise.
Change-Id: I01b2eba2e1be6cde59cad5a987978a412610a145
-rw-r--r-- | gcc/config/aarch64/aarch64.c | 55 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-init-1.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-init-2.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-init-3.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-init-4.c | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-init-5.c | 12 |
6 files changed, 111 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c76984c779d..80a1a802b8a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11715,6 +11715,57 @@ aarch64_expand_vector_init (rtx target, rtx vals) return; } + enum insn_code icode = optab_handler (vec_set_optab, mode); + gcc_assert (icode != CODE_FOR_nothing); + + /* If there are only variable elements, try to optimize + the insertion using dup for the most common element + followed by insertions. */ + + /* The algorithm will fill matches[*][0] with the earliest matching element, + and matches[X][1] with the count of duplicate elements (if X is the + earliest element which has duplicates). */ + + if (n_var == n_elts && n_elts <= 16) + { + int matches[16][2] = {0}; + for (int i = 0; i < n_elts; i++) + { + for (int j = 0; j <= i; j++) + { + if (rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, j))) + { + matches[i][0] = j; + matches[j][1]++; + break; + } + } + } + int maxelement = 0; + int maxv = 0; + for (int i = 0; i < n_elts; i++) + if (matches[i][1] > maxv) + { + maxelement = i; + maxv = matches[i][1]; + } + + /* Create a duplicate of the most common element. */ + rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement)); + aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x)); + + /* Insert the rest. */ + for (int i = 0; i < n_elts; i++) + { + rtx x = XVECEXP (vals, 0, i); + if (matches[i][0] == maxelement) + continue; + x = copy_to_mode_reg (inner_mode, x); + emit_insn (GEN_FCN (icode) (target, x, GEN_INT (i))); + } + return; + } + /* Initialise a vector which is part-variable. We want to first try to build those lanes which are constant in the most efficient way we can. */ @@ -11748,10 +11799,6 @@ aarch64_expand_vector_init (rtx target, rtx vals) } /* Insert the variable lanes directly. */ - - enum insn_code icode = optab_handler (vec_set_optab, mode); - gcc_assert (icode != CODE_FOR_nothing); - for (int i = 0; i < n_elts; i++) { rtx x = XVECEXP (vals, 0, i); diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-1.c b/gcc/testsuite/gcc.target/aarch64/vect-init-1.c new file mode 100644 index 00000000000..90ba3ae3b99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float c, float d) +{ + return (vector float) { a, b, c, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-2.c b/gcc/testsuite/gcc.target/aarch64/vect-init-2.c new file mode 100644 index 00000000000..04446754cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float d) +{ + return (vector float) { a, b, a, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-3.c b/gcc/testsuite/gcc.target/aarch64/vect-init-3.c new file mode 100644 index 00000000000..b5822b7fcb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, a, b }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-4.c b/gcc/testsuite/gcc.target/aarch64/vect-init-4.c new file mode 100644 index 00000000000..09a00958f14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, b, a }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-5.c b/gcc/testsuite/gcc.target/aarch64/vect-init-5.c new file mode 100644 index 00000000000..76d5502d54b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, a, a }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ |