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authorChristophe Lyon <christophe.lyon@linaro.org>2016-06-08 14:32:41 +0200
committerYvan Roux <yvan.roux@linaro.org>2016-06-14 13:32:05 +0000
commit1f4098872e983839005d56c080d00ba94356657e (patch)
tree4cc77561e40c3c5d6e072846f0df23e92007ef29
parent2abcccf993e073a759a8a55493c5da4bddd2e23b (diff)
gcc/
Backport from trunk r236984. 2016-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/sync.md (arm_store_exclusive<mode>): Use 'H' output modifier on operands[2] rather than creating a new entry in out-of-bounds memory of the operands array. (arm_store_release_exclusivedi): Likewise. Change-Id: I37d221771a13a79ff59554c1fbf250dcaf95c14d
-rw-r--r--gcc/config/arm/sync.md15
1 files changed, 6 insertions, 9 deletions
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 0589e4d8905..abcfbcb1eac 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -452,14 +452,13 @@
{
if (<MODE>mode == DImode)
{
- rtx value = operands[2];
/* The restrictions on target registers in ARM mode are that the two
registers are consecutive and the first one is even; Thumb is
actually more flexible, but DI should give us this anyway.
- Note that the 1st register always gets the lowest word in memory. */
- gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
- operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
- return "strexd%?\t%0, %2, %3, %C1";
+ Note that the 1st register always gets the
+ lowest word in memory. */
+ gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
+ return "strexd%?\t%0, %2, %H2, %C1";
}
return "strex<sync_sfx>%?\t%0, %2, %C1";
}
@@ -475,11 +474,9 @@
VUNSPEC_SLX))]
"TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
{
- rtx value = operands[2];
/* See comment in arm_store_exclusive<mode> above. */
- gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
- operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
- return "stlexd%?\t%0, %2, %3, %C1";
+ gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
+ return "stlexd%?\t%0, %2, %H2, %C1";
}
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])