diff options
| author | Yvan Roux <yvan.roux@linaro.org> | 2017-07-04 16:33:32 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2017-07-05 07:09:52 +0000 |
| commit | e2a372935b818724d38271fce10f8d66a6084bf8 (patch) | |
| tree | 04e854b2e17bd9fe701b920d0d3b612323fe0d1c | |
| parent | 997d96a83dc7bd109432b35439f70e1e1d2de60f (diff) | |
gcc/
Backport from trunk r248949.
2017-06-07 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md
(copysignsf3): Fix mask generation.
Change-Id: Idcb0fb6c0d588373bd3aaf71e172524e27023d94
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 475c6d7e85d..edf9373ac13 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4942,14 +4942,16 @@ (match_operand:SF 2 "register_operand")] "TARGET_FLOAT && TARGET_SIMD" { - rtx mask = gen_reg_rtx (DImode); + rtx v_bitmask = gen_reg_rtx (V2SImode); /* Juggle modes to get us in to a vector mode for BSL. */ - rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode); + rtx op1 = lowpart_subreg (DImode, operands[1], SFmode); rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode); rtx tmp = gen_reg_rtx (V2SFmode); - emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31)); - emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1)); + emit_move_insn (v_bitmask, + aarch64_simd_gen_const_vector_dup (V2SImode, + HOST_WIDE_INT_M1U << 31)); + emit_insn (gen_aarch64_simd_bslv2sf (tmp, v_bitmask, op2, op1)); emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode)); DONE; } |