diff options
| author | Backport Tool <christophe.lyon@linaro.org> | 2016-01-28 13:32:52 +0100 |
|---|---|---|
| committer | Linaro Code Review <review@review.linaro.org> | 2016-02-04 09:46:30 +0000 |
| commit | 5cde97d413185eb7f0b52ef324ed0573aac2e63b (patch) | |
| tree | 255a69d06164836cf2223c572827d1c4d7c4f15a | |
| parent | df7e22a143d4246ee728ff46a5552dfa2b6811c8 (diff) | |
gcc/
Backport from trunk r232921.
2016-01-28 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.md (ccmp<mode>): Disassemble
immediate as %1.
(add<mode>3_compare0): Likewise.
(addsi3_compare0_uxtw): Likewise.
(add<mode>3nr_compare0): Likewise.
(compare_neg<mode>): Likewise.
(<optab><mode>3): Likewise.
Change-Id: Ife9f84d09d1d04b486408a290c4bb067c0cf42af
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 0eb10c49f54..e946b23ec52 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -279,7 +279,7 @@ "aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])" "@ ccmp\\t%<w>2, %<w>3, %k5, %m4 - ccmp\\t%<w>2, %<w>3, %k5, %m4 + ccmp\\t%<w>2, %3, %k5, %m4 ccmn\\t%<w>2, #%n3, %k5, %m4" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -1726,7 +1726,7 @@ "" "@ adds\\t%<w>0, %<w>1, %<w>2 - adds\\t%<w>0, %<w>1, %<w>2 + adds\\t%<w>0, %<w>1, %2 subs\\t%<w>0, %<w>1, #%n2" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -1743,7 +1743,7 @@ "" "@ adds\\t%w0, %w1, %w2 - adds\\t%w0, %w1, %w2 + adds\\t%w0, %w1, %2 subs\\t%w0, %w1, #%n2" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -1925,7 +1925,7 @@ "" "@ cmn\\t%<w>0, %<w>1 - cmn\\t%<w>0, %<w>1 + cmn\\t%<w>0, %1 cmp\\t%<w>0, #%n1" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -2871,7 +2871,7 @@ "" "@ cmp\\t%<w>0, %<w>1 - cmp\\t%<w>0, %<w>1 + cmp\\t%<w>0, %1 cmn\\t%<w>0, #%n1" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -3291,7 +3291,7 @@ "" "@ <logical>\\t%<w>0, %<w>1, %<w>2 - <logical>\\t%<w>0, %<w>1, %<w>2 + <logical>\\t%<w>0, %<w>1, %2 <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" [(set_attr "type" "logic_reg,logic_imm,neon_logic") (set_attr "simd" "*,*,yes")] |