[AArch64] PR63870 Improve error messages for NEON single lane memory alinaro-local/cbaylis-test1

ccess intrinsics

gcc/ChangeLog:

<DATE>  Charles Baylis  <charles.baylis@linaro.org>

	PR target/63870
	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
	Add qualifier_struct_load_store_lane_index.
	(aarch64_types_loadstruct_lane_qualifiers): Use
	qualifier_struct_load_store_lane_index for lane index argument for
	last argument.
	(aarch64_types_storestruct_lane_qualifiers): Ditto.
	(builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_args): Add new argument describing mode of
	builtin. Check lane bounds for arguments with
	SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_builtin): Emit error for incorrect lane indices
	if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
	(aarch64_simd_expand_builtin): Handle arguments with
	qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
	aarch64_simd_expand_args.
	* config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
	vst[234]_lane with BUILTIN_VALLDIF.
	* config/aarch64/aarch64-simd.md:
	(aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
	endianness reversal on lane index.
	(aarch64_vec_load_lanesci_lane<mode>): Ditto.
	(aarch64_vec_load_lanesxi_lane<mode>): Ditto.
	(vec_store_lanesoi_lane<mode>): Use VALLDIF iterator. Fix typo
	in attribute.
	(vec_store_lanesci_lane<mode>): Use VALLDIF iterator.
	(vec_store_lanesxi_lane<mode>): Ditto.
	(aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
	reversal of lane index.
	(aarch64_ld3_lane<mode>): Ditto.
	(aarch64_ld4_lane<mode>): Ditto.
	(aarch64_st2_lane<mode>): Ditto.
	(aarch64_st3_lane<mode>): Ditto.
	(aarch64_st4_lane<mode>): Ditto.
	* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
	to qmode. Add new mode parameter. Update uses.
       	(__LD3_LANE_FUNC): Ditto.
	(__LD4_LANE_FUNC): Ditto.
	(__ST2_LANE_FUNC): Ditto.
	(__ST3_LANE_FUNC): Ditto.
	(__ST4_LANE_FUNC): Ditto.

gcc/testsuite/ChangeLog:

<DATE>  Charles Baylis  <charles.baylis@linaro.org>

	* gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c: New test.
	* gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c: New test.

Change-Id: Ib17adaf64e631cf8d00a1a1a6c12409d2d7f4239

136 files changed, 1529 insertions, 177 deletions

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 5c324b8dd7e..a1ed6fcdecf 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -128,7 +128,9 @@ enum aarch64_type_qualifiers
   /* Polynomial types.  */
   qualifier_poly = 0x100,
   /* Lane indices - must be in range, and flipped for bigendian.  */
-  qualifier_lane_index = 0x200
+  qualifier_lane_index = 0x200,
+  /* Lane indices for single lane structure loads and stores */
+  qualifier_struct_load_store_lane_index = 0x400
 };
 
 typedef struct
@@ -230,7 +232,7 @@ aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 static enum aarch64_type_qualifiers
 aarch64_types_loadstruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_const_pointer_map_mode,
-      qualifier_none, qualifier_none };
+      qualifier_none, qualifier_struct_load_store_lane_index };
 #define TYPES_LOADSTRUCT_LANE (aarch64_types_loadstruct_lane_qualifiers)
 
 static enum aarch64_type_qualifiers
@@ -262,7 +264,7 @@ aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 static enum aarch64_type_qualifiers
 aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_void, qualifier_pointer_map_mode,
-      qualifier_none, qualifier_none };
+      qualifier_none, qualifier_struct_load_store_lane_index };
 #define TYPES_STORESTRUCT_LANE (aarch64_types_storestruct_lane_qualifiers)
 
 #define CF0(N, X) CODE_FOR_aarch64_##N##X
@@ -878,12 +880,14 @@ typedef enum
   SIMD_ARG_COPY_TO_REG,
   SIMD_ARG_CONSTANT,
   SIMD_ARG_LANE_INDEX,
+  SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
   SIMD_ARG_STOP
 } builtin_simd_arg;
 
 static rtx
 aarch64_simd_expand_args (rtx target, int icode, int have_retval,
-			  tree exp, builtin_simd_arg *args)
+			  tree exp, builtin_simd_arg *args,
+			  enum machine_mode builtin_mode)
 {
   rtx pat;
   rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand.  */
@@ -922,6 +926,19 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
 		op[opc] = copy_to_mode_reg (mode, op[opc]);
 	      break;
 
+	    case SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX:
+	      gcc_assert (opc > 1);
+	      if (CONST_INT_P (op[opc]))
+		{
+		  aarch64_simd_lane_bounds (op[opc], 0,
+					    GET_MODE_NUNITS (builtin_mode),
+					    exp);
+		  /* Keep to GCC-vector-extension lane indices in the RTL.  */
+		  op[opc] =
+		    GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc])));
+		}
+	      goto constant_arg;
+
 	    case SIMD_ARG_LANE_INDEX:
 	      /* Must be a previous operand into which this is an index.  */
 	      gcc_assert (opc > 0);
@@ -936,6 +953,7 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
 	      /* Fall through - if the lane index isn't a constant then
 		 the next case will error.  */
 	    case SIMD_ARG_CONSTANT:
+constant_arg:
 	      if (!(*insn_data[icode].operand[opc].predicate)
 		  (op[opc], mode))
 	      {
@@ -1044,6 +1062,8 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
 
       if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
 	args[k] = SIMD_ARG_LANE_INDEX;
+      else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
+	args[k] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
       else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
 	args[k] = SIMD_ARG_CONSTANT;
       else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
@@ -1067,7 +1087,7 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target)
   /* The interface to aarch64_simd_expand_args expects a 0 if
      the function is void, and a 1 if it is not.  */
   return aarch64_simd_expand_args
-	  (target, icode, !is_void, exp, &args[1]);
+	  (target, icode, !is_void, exp, &args[1], d->mode);
 }
 
 rtx
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index dd2bc47ae1e..d0f298a1f07 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -88,9 +88,9 @@
   BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
   BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
   /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>.  */
-  BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0)
-  BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0)
-  BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0)
+  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0)
+  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0)
+  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0)
   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
   BUILTIN_VDC (STORESTRUCT, st2, 0)
   BUILTIN_VDC (STORESTRUCT, st3, 0)
@@ -100,9 +100,9 @@
   BUILTIN_VQ (STORESTRUCT, st3, 0)
   BUILTIN_VQ (STORESTRUCT, st4, 0)
 
-  BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
-  BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
-  BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
+  BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0)
+  BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0)
+  BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0)
 
   BUILTIN_VQW (BINOP, saddl2, 0)
   BUILTIN_VQW (BINOP, uaddl2, 0)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b90f93841f8..7346e74b91e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3919,10 +3919,13 @@
 	(unspec:OI [(match_operand:<V_TWO_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
 		    (match_operand:OI 2 "register_operand" "0")
 		    (match_operand:SI 3 "immediate_operand" "i")
-		    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
+		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
 		   UNSPEC_LD2_LANE))]
   "TARGET_SIMD"
-  "ld2\\t{%S0.<Vetype> - %T0.<Vetype>}[%3], %1"
+  {
+    operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
+    return "ld2\\t{%S0.<Vetype> - %T0.<Vetype>}[%3], %1";
+  }
   [(set_attr "type" "neon_load2_one_lane")]
 )
 
@@ -3959,7 +3962,7 @@
 (define_insn "vec_store_lanesoi_lane<mode>"
   [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
 	(unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w")
-                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+                    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
 		    (match_operand:SI 2 "immediate_operand" "i")]
                    UNSPEC_ST2_LANE))]
   "TARGET_SIMD"
@@ -3967,7 +3970,7 @@
     operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
     return "st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0";
   }
-  [(set_attr "type" "neon_store3_one_lane<q>")]
+  [(set_attr "type" "neon_store2_one_lane<q>")]
 )
 
 (define_expand "vec_store_lanesoi<mode>"
@@ -4014,10 +4017,13 @@
 	(unspec:CI [(match_operand:<V_THREE_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
 		    (match_operand:CI 2 "register_operand" "0")
 		    (match_operand:SI 3 "immediate_operand" "i")
-		    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
 		   UNSPEC_LD3_LANE))]
   "TARGET_SIMD"
-  "ld3\\t{%S0.<Vetype> - %U0.<Vetype>}[%3], %1"
+{
+    operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
+    return "ld3\\t{%S0.<Vetype> - %U0.<Vetype>}[%3], %1";
+}
   [(set_attr "type" "neon_load3_one_lane")]
 )
 
@@ -4054,7 +4060,7 @@
 (define_insn "vec_store_lanesci_lane<mode>"
   [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
 	(unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w")
-                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+                    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
 		    (match_operand:SI 2 "immediate_operand" "i")]
                    UNSPEC_ST3_LANE))]
   "TARGET_SIMD"
@@ -4109,10 +4115,13 @@
 	(unspec:XI [(match_operand:<V_FOUR_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
 		    (match_operand:XI 2 "register_operand" "0")
 		    (match_operand:SI 3 "immediate_operand" "i")
-		    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
 		   UNSPEC_LD4_LANE))]
   "TARGET_SIMD"
-  "ld4\\t{%S0.<Vetype> - %V0.<Vetype>}[%3], %1"
+{
+    operands[3] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3])));
+    return "ld4\\t{%S0.<Vetype> - %V0.<Vetype>}[%3], %1";
+}
   [(set_attr "type" "neon_load4_one_lane")]
 )
 
@@ -4149,7 +4158,7 @@
 (define_insn "vec_store_lanesxi_lane<mode>"
   [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
 	(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
-                    (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+                    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
 		    (match_operand:SI 2 "immediate_operand" "i")]
                    UNSPEC_ST4_LANE))]
   "TARGET_SIMD"
@@ -4566,14 +4575,12 @@
 	(match_operand:DI 1 "register_operand" "w")
 	(match_operand:OI 2 "register_operand" "0")
 	(match_operand:SI 3 "immediate_operand" "i")
-	(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+	(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
   machine_mode mode = <V_TWO_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[1]);
 
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
-			    NULL);
   emit_insn (gen_aarch64_vec_load_lanesoi_lane<mode> (operands[0],
 						      mem,
 						      operands[2],
@@ -4586,14 +4593,12 @@
 	(match_operand:DI 1 "register_operand" "w")
 	(match_operand:CI 2 "register_operand" "0")
 	(match_operand:SI 3 "immediate_operand" "i")
-	(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+	(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
   machine_mode mode = <V_THREE_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[1]);
 
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
-			    NULL);
   emit_insn (gen_aarch64_vec_load_lanesci_lane<mode> (operands[0],
 						      mem,
 						      operands[2],
@@ -4606,14 +4611,12 @@
 	(match_operand:DI 1 "register_operand" "w")
 	(match_operand:XI 2 "register_operand" "0")
 	(match_operand:SI 3 "immediate_operand" "i")
-	(unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+	(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
   machine_mode mode = <V_FOUR_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[1]);
 
-  aarch64_simd_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<VCONQ>mode),
-			    NULL);
   emit_insn (gen_aarch64_vec_load_lanesxi_lane<mode> (operands[0],
 						      mem,
 						      operands[2],
@@ -4850,54 +4853,45 @@
   DONE;
 })
 
-(define_expand "aarch64_st2_lane<VQ:mode>"
+(define_expand "aarch64_st2_lane<mode>"
  [(match_operand:DI 0 "register_operand" "r")
   (match_operand:OI 1 "register_operand" "w")
-  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+  (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
   (match_operand:SI 2 "immediate_operand")]
   "TARGET_SIMD"
 {
   machine_mode mode = <V_TWO_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[0]);
-  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
 
-  emit_insn (gen_vec_store_lanesoi_lane<VQ:mode> (mem,
-						  operands[1],
-						  operands[2]));
+  emit_insn (gen_vec_store_lanesoi_lane<mode> (mem, operands[1], operands[2]));
   DONE;
 })
 
-(define_expand "aarch64_st3_lane<VQ:mode>"
+(define_expand "aarch64_st3_lane<mode>"
  [(match_operand:DI 0 "register_operand" "r")
   (match_operand:CI 1 "register_operand" "w")
-  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+  (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
   (match_operand:SI 2 "immediate_operand")]
   "TARGET_SIMD"
 {
   machine_mode mode = <V_THREE_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[0]);
-  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
 
-  emit_insn (gen_vec_store_lanesci_lane<VQ:mode> (mem,
-						  operands[1],
-						  operands[2]));
+  emit_insn (gen_vec_store_lanesci_lane<mode> (mem, operands[1], operands[2]));
   DONE;
 })
 
-(define_expand "aarch64_st4_lane<VQ:mode>"
+(define_expand "aarch64_st4_lane<mode>"
  [(match_operand:DI 0 "register_operand" "r")
   (match_operand:XI 1 "register_operand" "w")
-  (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+  (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
   (match_operand:SI 2 "immediate_operand")]
   "TARGET_SIMD"
 {
   machine_mode mode = <V_FOUR_ELEM>mode;
   rtx mem = gen_rtx_MEM (mode, operands[0]);
-  operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
 
-  emit_insn (gen_vec_store_lanesxi_lane<VQ:mode> (mem,
-						  operands[1],
-						  operands[2]));
+  emit_insn (gen_vec_store_lanesxi_lane<mode> (mem, operands[1], operands[2]));
   DONE;
 })
 
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 114994e48b7..fce557779c2 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -9950,8 +9950,8 @@ __STRUCTN (float, 64, 4)
 #undef __STRUCTN
 
 
-#define __ST2_LANE_FUNC(intype, largetype, ptrtype,			     \
-			mode, ptr_mode, funcsuffix, signedtype)		     \
+#define __ST2_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+			qmode, ptr_mode, funcsuffix, signedtype)	     \
 __extension__ static __inline void					     \
 __attribute__ ((__always_inline__))					     \
 vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
@@ -9965,31 +9965,37 @@ vst2_lane_ ## funcsuffix (ptrtype *__ptr,				     \
   __temp.val[1]								     \
     = vcombine_##funcsuffix (__b.val[1],				     \
 			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-  __o = __builtin_aarch64_set_qregoi##mode (__o,			     \
-					    (signedtype) __temp.val[0], 0);  \
-  __o = __builtin_aarch64_set_qregoi##mode (__o,			     \
-					    (signedtype) __temp.val[1], 1);  \
+  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
+					     (signedtype) __temp.val[0], 0); \
+  __o = __builtin_aarch64_set_qregoi##qmode (__o,			     \
+					     (signedtype) __temp.val[1], 1); \
   __builtin_aarch64_st2_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
 				     __ptr, __o, __c);			     \
 }
 
-__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v4sf, sf, f32,
+__ST2_LANE_FUNC (float32x2x2_t, float32x4x2_t, float32_t, v2sf, v4sf, sf, f32,
 		 float32x4_t)
-__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, v2df, df, f64,
+__ST2_LANE_FUNC (float64x1x2_t, float64x2x2_t, float64_t, df, v2df, df, f64,
 		 float64x2_t)
-__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v16qi, qi, p8, int8x16_t)
-__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v8hi, hi, p16,
+__ST2_LANE_FUNC (poly8x8x2_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
+		 int8x16_t)
+__ST2_LANE_FUNC (poly16x4x2_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi, p16,
 		 int16x8_t)
-__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v16qi, qi, s8, int8x16_t)
-__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v8hi, hi, s16, int16x8_t)
-__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v4si, si, s32, int32x4_t)
-__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, v2di, di, s64, int64x2_t)
-__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v16qi, qi, u8, int8x16_t)
-__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v8hi, hi, u16,
+__ST2_LANE_FUNC (int8x8x2_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
+		 int8x16_t)
+__ST2_LANE_FUNC (int16x4x2_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
 		 int16x8_t)
-__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v4si, si, u32,
+__ST2_LANE_FUNC (int32x2x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
 		 int32x4_t)
-__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, v2di, di, u64,
+__ST2_LANE_FUNC (int64x1x2_t, int64x2x2_t, int64_t, di, v2di, di, s64,
+		 int64x2_t)
+__ST2_LANE_FUNC (uint8x8x2_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
+		 int8x16_t)
+__ST2_LANE_FUNC (uint16x4x2_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi, u16,
+		 int16x8_t)
+__ST2_LANE_FUNC (uint32x2x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si, u32,
+		 int32x4_t)
+__ST2_LANE_FUNC (uint64x1x2_t, uint64x2x2_t, uint64_t, di, v2di, di, u64,
 		 int64x2_t)
 
 #undef __ST2_LANE_FUNC
@@ -10018,8 +10024,8 @@ __ST2_LANE_FUNC (uint16x8x2_t, uint16_t, v8hi, hi, u16)
 __ST2_LANE_FUNC (uint32x4x2_t, uint32_t, v4si, si, u32)
 __ST2_LANE_FUNC (uint64x2x2_t, uint64_t, v2di, di, u64)
 
-#define __ST3_LANE_FUNC(intype, largetype, ptrtype,			     \
-			mode, ptr_mode, funcsuffix, signedtype)		     \
+#define __ST3_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+			qmode, ptr_mode, funcsuffix, signedtype)	     \
 __extension__ static __inline void					     \
 __attribute__ ((__always_inline__))					     \
 vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
@@ -10036,33 +10042,39 @@ vst3_lane_ ## funcsuffix (ptrtype *__ptr,				     \
   __temp.val[2]								     \
     = vcombine_##funcsuffix (__b.val[2],				     \
 			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-  __o = __builtin_aarch64_set_qregci##mode (__o,			     \
-					    (signedtype) __temp.val[0], 0);  \
-  __o = __builtin_aarch64_set_qregci##mode (__o,			     \
-					    (signedtype) __temp.val[1], 1);  \
-  __o = __builtin_aarch64_set_qregci##mode (__o,			     \
-					    (signedtype) __temp.val[2], 2);  \
+  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+					     (signedtype) __temp.val[0], 0); \
+  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+					     (signedtype) __temp.val[1], 1); \
+  __o = __builtin_aarch64_set_qregci##qmode (__o,			     \
+					     (signedtype) __temp.val[2], 2); \
   __builtin_aarch64_st3_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
 				     __ptr, __o, __c);			     \
 }
 
-__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v4sf, sf, f32,
+__ST3_LANE_FUNC (float32x2x3_t, float32x4x3_t, float32_t, v2sf, v4sf, sf, f32,
 		 float32x4_t)
-__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, v2df, df, f64,
+__ST3_LANE_FUNC (float64x1x3_t, float64x2x3_t, float64_t, df, v2df, df, f64,
 		 float64x2_t)
-__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v16qi, qi, p8, int8x16_t)
-__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v8hi, hi, p16,
+__ST3_LANE_FUNC (poly8x8x3_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
+		 int8x16_t)
+__ST3_LANE_FUNC (poly16x4x3_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi, p16,
+		 int16x8_t)
+__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
+		 int8x16_t)
+__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
 		 int16x8_t)
-__ST3_LANE_FUNC (int8x8x3_t, int8x16x3_t, int8_t, v16qi, qi, s8, int8x16_t)
-__ST3_LANE_FUNC (int16x4x3_t, int16x8x3_t, int16_t, v8hi, hi, s16, int16x8_t)
-__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v4si, si, s32, int32x4_t)
-__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, v2di, di, s64, int64x2_t)
-__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v16qi, qi, u8, int8x16_t)
-__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v8hi, hi, u16,
+__ST3_LANE_FUNC (int32x2x3_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
+		 int32x4_t)
+__ST3_LANE_FUNC (int64x1x3_t, int64x2x3_t, int64_t, di, v2di, di, s64,
+		 int64x2_t)
+__ST3_LANE_FUNC (uint8x8x3_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
+		 int8x16_t)
+__ST3_LANE_FUNC (uint16x4x3_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi, u16,
 		 int16x8_t)
-__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v4si, si, u32,
+__ST3_LANE_FUNC (uint32x2x3_t, uint32x4x3_t, uint32_t, v2si, v4si, si, u32,
 		 int32x4_t)
-__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, v2di, di, u64,
+__ST3_LANE_FUNC (uint64x1x3_t, uint64x2x3_t, uint64_t, di, v2di, di, u64,
 		 int64x2_t)
 
 #undef __ST3_LANE_FUNC
@@ -10091,8 +10103,8 @@ __ST3_LANE_FUNC (uint16x8x3_t, uint16_t, v8hi, hi, u16)
 __ST3_LANE_FUNC (uint32x4x3_t, uint32_t, v4si, si, u32)
 __ST3_LANE_FUNC (uint64x2x3_t, uint64_t, v2di, di, u64)
 
-#define __ST4_LANE_FUNC(intype, largetype, ptrtype,			     \
-			mode, ptr_mode, funcsuffix, signedtype)		     \
+#define __ST4_LANE_FUNC(intype, largetype, ptrtype, mode,		     \
+			qmode, ptr_mode, funcsuffix, signedtype)	     \
 __extension__ static __inline void					     \
 __attribute__ ((__always_inline__))					     \
 vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
@@ -10112,35 +10124,41 @@ vst4_lane_ ## funcsuffix (ptrtype *__ptr,				     \
   __temp.val[3]								     \
     = vcombine_##funcsuffix (__b.val[3],				     \
 			     vcreate_##funcsuffix (__AARCH64_UINT64_C (0))); \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-					    (signedtype) __temp.val[0], 0);  \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-					    (signedtype) __temp.val[1], 1);  \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-					    (signedtype) __temp.val[2], 2);  \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			     \
-					    (signedtype) __temp.val[3], 3);  \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+					     (signedtype) __temp.val[0], 0); \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+					     (signedtype) __temp.val[1], 1); \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+					     (signedtype) __temp.val[2], 2); \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			     \
+					     (signedtype) __temp.val[3], 3); \
   __builtin_aarch64_st4_lane##mode ((__builtin_aarch64_simd_ ## ptr_mode *)  \
 				     __ptr, __o, __c);			     \
 }
 
-__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v4sf, sf, f32,
+__ST4_LANE_FUNC (float32x2x4_t, float32x4x4_t, float32_t, v2sf, v4sf, sf, f32,
 		 float32x4_t)
-__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, v2df, df, f64,
+__ST4_LANE_FUNC (float64x1x4_t, float64x2x4_t, float64_t, df, v2df, df, f64,
 		 float64x2_t)
-__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v16qi, qi, p8, int8x16_t)
-__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v8hi, hi, p16,
+__ST4_LANE_FUNC (poly8x8x4_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
+		 int8x16_t)
+__ST4_LANE_FUNC (poly16x4x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi, p16,
 		 int16x8_t)
-__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v16qi, qi, s8, int8x16_t)
-__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v8hi, hi, s16, int16x8_t)
-__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v4si, si, s32, int32x4_t)
-__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, v2di, di, s64, int64x2_t)
-__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v16qi, qi, u8, int8x16_t)
-__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v8hi, hi, u16,
+__ST4_LANE_FUNC (int8x8x4_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
+		 int8x16_t)
+__ST4_LANE_FUNC (int16x4x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
+		 int16x8_t)
+__ST4_LANE_FUNC (int32x2x4_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
+		 int32x4_t)
+__ST4_LANE_FUNC (int64x1x4_t, int64x2x4_t, int64_t, di, v2di, di, s64,
+		 int64x2_t)
+__ST4_LANE_FUNC (uint8x8x4_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
+		 int8x16_t)
+__ST4_LANE_FUNC (uint16x4x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi, u16,
 		 int16x8_t)
-__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v4si, si, u32,
+__ST4_LANE_FUNC (uint32x2x4_t, uint32x4x4_t, uint32_t, v2si, v4si, si, u32,
 		 int32x4_t)
-__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, v2di, di, u64,
+__ST4_LANE_FUNC (uint64x1x4_t, uint64x2x4_t, uint64_t, di, v2di, di, u64,
 		 int64x2_t)
 
 #undef __ST4_LANE_FUNC
@@ -16799,8 +16817,8 @@ vld4q_dup_f64 (const float64_t * __a)
 
 /* vld2_lane */
 
-#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype,		   \
-			 mode, ptrmode, funcsuffix, signedtype)		   \
+#define __LD2_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+			 qmode, ptrmode, funcsuffix, signedtype)	   \
 __extension__ static __inline intype __attribute__ ((__always_inline__))   \
 vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
 {									   \
@@ -16810,12 +16828,12 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
     vcombine_##funcsuffix (__b.val[0], vcreate_##funcsuffix (0));	   \
   __temp.val[1] =							   \
     vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
-  __o = __builtin_aarch64_set_qregoi##mode (__o,			   \
-					   (signedtype) __temp.val[0],	   \
-					   0);				   \
-  __o = __builtin_aarch64_set_qregoi##mode (__o,			   \
-					   (signedtype) __temp.val[1],	   \
-					   1);				   \
+  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
+					    (signedtype) __temp.val[0],	   \
+					    0);				   \
+  __o = __builtin_aarch64_set_qregoi##qmode (__o,			   \
+					    (signedtype) __temp.val[1],	   \
+					    1);				   \
   __o =	__builtin_aarch64_ld2_lane##mode (				   \
 	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
   __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0);	   \
@@ -16823,29 +16841,29 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
   return __b;								   \
 }
 
-__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v4sf,
+__LD2_LANE_FUNC (float32x2x2_t, float32x2_t, float32x4x2_t, float32_t, v2sf, v4sf,
 		 sf, f32, float32x4_t)
-__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, v2df,
+__LD2_LANE_FUNC (float64x1x2_t, float64x1_t, float64x2x2_t, float64_t, df, v2df,
 		 df, f64, float64x2_t)
-__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v16qi, qi, p8,
+__LD2_LANE_FUNC (poly8x8x2_t, poly8x8_t, poly8x16x2_t, poly8_t, v8qi, v16qi, qi, p8,
 		 int8x16_t)
-__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v8hi, hi,
+__LD2_LANE_FUNC (poly16x4x2_t, poly16x4_t, poly16x8x2_t, poly16_t, v4hi, v8hi, hi,
 		 p16, int16x8_t)
-__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v16qi, qi, s8,
+__LD2_LANE_FUNC (int8x8x2_t, int8x8_t, int8x16x2_t, int8_t, v8qi, v16qi, qi, s8,
 		 int8x16_t)
-__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v8hi, hi, s16,
+__LD2_LANE_FUNC (int16x4x2_t, int16x4_t, int16x8x2_t, int16_t, v4hi, v8hi, hi, s16,
 		 int16x8_t)
-__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v4si, si, s32,
+__LD2_LANE_FUNC (int32x2x2_t, int32x2_t, int32x4x2_t, int32_t, v2si, v4si, si, s32,
 		 int32x4_t)
-__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, v2di, di, s64,
+__LD2_LANE_FUNC (int64x1x2_t, int64x1_t, int64x2x2_t, int64_t, di, v2di, di, s64,
 		 int64x2_t)
-__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v16qi, qi, u8,
+__LD2_LANE_FUNC (uint8x8x2_t, uint8x8_t, uint8x16x2_t, uint8_t, v8qi, v16qi, qi, u8,
 		 int8x16_t)
-__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v8hi, hi,
+__LD2_LANE_FUNC (uint16x4x2_t, uint16x4_t, uint16x8x2_t, uint16_t, v4hi, v8hi, hi,
 		 u16, int16x8_t)
-__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v4si, si,
+__LD2_LANE_FUNC (uint32x2x2_t, uint32x2_t, uint32x4x2_t, uint32_t, v2si, v4si, si,
 		 u32, int32x4_t)
-__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, v2di, di,
+__LD2_LANE_FUNC (uint64x1x2_t, uint64x1_t, uint64x2x2_t, uint64_t, di, v2di, di,
 		 u64, int64x2_t)
 
 #undef __LD2_LANE_FUNC
@@ -16884,8 +16902,8 @@ __LD2_LANE_FUNC (uint64x2x2_t, uint64x2_t, uint64_t, v2di, di, u64)
 
 /* vld3_lane */
 
-#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype,		   \
-			 mode, ptrmode, funcsuffix, signedtype)		   \
+#define __LD3_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+			 qmode, ptrmode, funcsuffix, signedtype)	   \
 __extension__ static __inline intype __attribute__ ((__always_inline__))   \
 vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
 {									   \
@@ -16897,15 +16915,15 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
     vcombine_##funcsuffix (__b.val[1], vcreate_##funcsuffix (0));	   \
   __temp.val[2] =							   \
     vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
-  __o = __builtin_aarch64_set_qregci##mode (__o,			   \
-					   (signedtype) __temp.val[0],	   \
-					   0);				   \
-  __o = __builtin_aarch64_set_qregci##mode (__o,			   \
-					   (signedtype) __temp.val[1],	   \
-					   1);				   \
-  __o = __builtin_aarch64_set_qregci##mode (__o,			   \
-					   (signedtype) __temp.val[2],	   \
-					   2);				   \
+  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+					    (signedtype) __temp.val[0],	   \
+					    0);				   \
+  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+					    (signedtype) __temp.val[1],	   \
+					    1);				   \
+  __o = __builtin_aarch64_set_qregci##qmode (__o,			   \
+					    (signedtype) __temp.val[2],	   \
+					    2);				   \
   __o =	__builtin_aarch64_ld3_lane##mode (				   \
 	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
   __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0);	   \
@@ -16914,29 +16932,29 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
   return __b;								   \
 }
 
-__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v4sf,
+__LD3_LANE_FUNC (float32x2x3_t, float32x2_t, float32x4x3_t, float32_t, v2sf, v4sf,
 		 sf, f32, float32x4_t)
-__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, v2df,
+__LD3_LANE_FUNC (float64x1x3_t, float64x1_t, float64x2x3_t, float64_t, df, v2df,
 		 df, f64, float64x2_t)
-__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v16qi, qi, p8,
+__LD3_LANE_FUNC (poly8x8x3_t, poly8x8_t, poly8x16x3_t, poly8_t, v8qi, v16qi, qi, p8,
 		 int8x16_t)
-__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v8hi, hi,
+__LD3_LANE_FUNC (poly16x4x3_t, poly16x4_t, poly16x8x3_t, poly16_t, v4hi, v8hi, hi,
 		 p16, int16x8_t)
-__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v16qi, qi, s8,
+__LD3_LANE_FUNC (int8x8x3_t, int8x8_t, int8x16x3_t, int8_t, v8qi, v16qi, qi, s8,
 		 int8x16_t)
-__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v8hi, hi, s16,
+__LD3_LANE_FUNC (int16x4x3_t, int16x4_t, int16x8x3_t, int16_t, v4hi, v8hi, hi, s16,
 		 int16x8_t)
-__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v4si, si, s32,
+__LD3_LANE_FUNC (int32x2x3_t, int32x2_t, int32x4x3_t, int32_t, v2si, v4si, si, s32,
 		 int32x4_t)
-__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, v2di, di, s64,
+__LD3_LANE_FUNC (int64x1x3_t, int64x1_t, int64x2x3_t, int64_t, di, v2di, di, s64,
 		 int64x2_t)
-__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v16qi, qi, u8,
+__LD3_LANE_FUNC (uint8x8x3_t, uint8x8_t, uint8x16x3_t, uint8_t, v8qi, v16qi, qi, u8,
 		 int8x16_t)
-__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v8hi, hi,
+__LD3_LANE_FUNC (uint16x4x3_t, uint16x4_t, uint16x8x3_t, uint16_t, v4hi, v8hi, hi,
 		 u16, int16x8_t)
-__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v4si, si,
+__LD3_LANE_FUNC (uint32x2x3_t, uint32x2_t, uint32x4x3_t, uint32_t, v2si, v4si, si,
 		 u32, int32x4_t)
-__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, v2di, di,
+__LD3_LANE_FUNC (uint64x1x3_t, uint64x1_t, uint64x2x3_t, uint64_t, di, v2di, di,
 		 u64, int64x2_t)
 
 #undef __LD3_LANE_FUNC
@@ -16977,8 +16995,8 @@ __LD3_LANE_FUNC (uint64x2x3_t, uint64x2_t, uint64_t, v2di, di, u64)
 
 /* vld4_lane */
 
-#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype,		   \
-			 mode, ptrmode, funcsuffix, signedtype)		   \
+#define __LD4_LANE_FUNC(intype, vectype, largetype, ptrtype, mode,	   \
+			 qmode, ptrmode, funcsuffix, signedtype)	   \
 __extension__ static __inline intype __attribute__ ((__always_inline__))   \
 vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
 {									   \
@@ -16992,18 +17010,18 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
     vcombine_##funcsuffix (__b.val[2], vcreate_##funcsuffix (0));	   \
   __temp.val[3] =							   \
     vcombine_##funcsuffix (__b.val[3], vcreate_##funcsuffix (0));	   \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			   \
-					   (signedtype) __temp.val[0],	   \
-					   0);				   \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			   \
-					   (signedtype) __temp.val[1],	   \
-					   1);				   \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			   \
-					   (signedtype) __temp.val[2],	   \
-					   2);				   \
-  __o = __builtin_aarch64_set_qregxi##mode (__o,			   \
-					   (signedtype) __temp.val[3],	   \
-					   3);				   \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+					    (signedtype) __temp.val[0],	   \
+					    0);				   \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+					    (signedtype) __temp.val[1],	   \
+					    1);				   \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+					    (signedtype) __temp.val[2],	   \
+					    2);				   \
+  __o = __builtin_aarch64_set_qregxi##qmode (__o,			   \
+					    (signedtype) __temp.val[3],	   \
+					    3);				   \
   __o =	__builtin_aarch64_ld4_lane##mode (				   \
 	  (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c);	   \
   __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0);	   \
@@ -17015,29 +17033,29 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c)  \
 
 /* vld4q_lane */
 
-__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v4sf,
+__LD4_LANE_FUNC (float32x2x4_t, float32x2_t, float32x4x4_t, float32_t, v2sf, v4sf,
 		 sf, f32, float32x4_t)
-__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, v2df,
+__LD4_LANE_FUNC (float64x1x4_t, float64x1_t, float64x2x4_t, float64_t, df, v2df,
 		 df, f64, float64x2_t)
-__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v16qi, qi, p8,
+__LD4_LANE_FUNC (poly8x8x4_t, poly8x8_t, poly8x16x4_t, poly8_t, v8qi, v16qi, qi, p8,
 		 int8x16_t)
-__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v8hi, hi,
+__LD4_LANE_FUNC (poly16x4x4_t, poly16x4_t, poly16x8x4_t, poly16_t, v4hi, v8hi, hi,
 		 p16, int16x8_t)
-__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v16qi, qi, s8,
+__LD4_LANE_FUNC (int8x8x4_t, int8x8_t, int8x16x4_t, int8_t, v8qi, v16qi, qi, s8,
 		 int8x16_t)
-__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v8hi, hi, s16,
+__LD4_LANE_FUNC (int16x4x4_t, int16x4_t, int16x8x4_t, int16_t, v4hi, v8hi, hi, s16,
 		 int16x8_t)
-__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v4si, si, s32,
+__LD4_LANE_FUNC (int32x2x4_t, int32x2_t, int32x4x4_t, int32_t, v2si, v4si, si, s32,
 		 int32x4_t)
-__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, v2di, di, s64,
+__LD4_LANE_FUNC (int64x1x4_t, int64x1_t, int64x2x4_t, int64_t, di, v2di, di, s64,
 		 int64x2_t)
-__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v16qi, qi, u8,
+__LD4_LANE_FUNC (uint8x8x4_t, uint8x8_t, uint8x16x4_t, uint8_t, v8qi, v16qi, qi, u8,
 		 int8x16_t)
-__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v8hi, hi,
+__LD4_LANE_FUNC (uint16x4x4_t, uint16x4_t, uint16x8x4_t, uint16_t, v4hi, v8hi, hi,
 		 u16, int16x8_t)
-__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v4si, si,
+__LD4_LANE_FUNC (uint32x2x4_t, uint32x2_t, uint32x4x4_t, uint32_t, v2si, v4si, si,
 		 u32, int32x4_t)
-__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, v2di, di,
+__LD4_LANE_FUNC (uint64x1x4_t, uint64x1_t, uint64x2x4_t, uint64_t, di, v2di, di,
 		 u64, int64x2_t)
 
 #undef __LD4_LANE_FUNC
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c
new file mode 100644
index 00000000000..a61813bb45a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float32x2x2_t
+f_vld2_lane_f32 (float32_t * p, float32x2x2_t v)
+{
+  float32x2x2_t res;
+  res = vld2_lane_f32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld2_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c
new file mode 100644
index 00000000000..4938fd3c04e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float64x1x2_t
+f_vld2_lane_f64 (float64_t * p, float64x1x2_t v)
+{
+  float64x1x2_t res;
+  res = vld2_lane_f64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld2_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c
new file mode 100644
index 00000000000..496602fb2de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+poly8x8x2_t
+f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v)
+{
+  poly8x8x2_t res;
+  res = vld2_lane_p8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld2_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c
new file mode 100644
index 00000000000..435714df612
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int16x4x2_t
+f_vld2_lane_s16 (int16_t * p, int16x4x2_t v)
+{
+  int16x4x2_t res;
+  res = vld2_lane_s16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld2_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c
new file mode 100644
index 00000000000..8711af2b1a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int32x2x2_t
+f_vld2_lane_s32 (int32_t * p, int32x2x2_t v)
+{
+  int32x2x2_t res;
+  res = vld2_lane_s32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld2_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c
new file mode 100644
index 00000000000..36a9d9d40dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int64x1x2_t
+f_vld2_lane_s64 (int64_t * p, int64x1x2_t v)
+{
+  int64x1x2_t res;
+  res = vld2_lane_s64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld2_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c
new file mode 100644
index 00000000000..8fe03220945
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int8x8x2_t
+f_vld2_lane_s8 (int8_t * p, int8x8x2_t v)
+{
+  int8x8x2_t res;
+  res = vld2_lane_s8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld2_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c
new file mode 100644
index 00000000000..8747f813688
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint16x4x2_t
+f_vld2_lane_u16 (uint16_t * p, uint16x4x2_t v)
+{
+  uint16x4x2_t res;
+  res = vld2_lane_u16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld2_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c
new file mode 100644
index 00000000000..db051192639
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint32x2x2_t
+f_vld2_lane_u32 (uint32_t * p, uint32x2x2_t v)
+{
+  uint32x2x2_t res;
+  res = vld2_lane_u32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld2_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c
new file mode 100644
index 00000000000..e13ec86c95d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint64x1x2_t
+f_vld2_lane_u64 (uint64_t * p, uint64x1x2_t v)
+{
+  uint64x1x2_t res;
+  res = vld2_lane_u64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld2_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c
new file mode 100644
index 00000000000..f565969a6ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint8x8x2_t
+f_vld2_lane_u8 (uint8_t * p, uint8x8x2_t v)
+{
+  uint8x8x2_t res;
+  res = vld2_lane_u8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld2_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c
new file mode 100644
index 00000000000..1b145e3c8c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float32x4x2_t
+f_vld2q_lane_f32 (float32_t * p, float32x4x2_t v)
+{
+  float32x4x2_t res;
+  res = vld2q_lane_f32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld2q_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c
new file mode 100644
index 00000000000..f66a309c3c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float64x2x2_t
+f_vld2q_lane_f64 (float64_t * p, float64x2x2_t v)
+{
+  float64x2x2_t res;
+  res = vld2q_lane_f64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld2q_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c
new file mode 100644
index 00000000000..5b3661d7a6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+poly8x16x2_t
+f_vld2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
+{
+  poly8x16x2_t res;
+  res = vld2q_lane_p8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld2q_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c
new file mode 100644
index 00000000000..6dcd8aedcdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int16x8x2_t
+f_vld2q_lane_s16 (int16_t * p, int16x8x2_t v)
+{
+  int16x8x2_t res;
+  res = vld2q_lane_s16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld2q_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c
new file mode 100644
index 00000000000..373c2e31db8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int32x4x2_t
+f_vld2q_lane_s32 (int32_t * p, int32x4x2_t v)
+{
+  int32x4x2_t res;
+  res = vld2q_lane_s32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld2q_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c
new file mode 100644
index 00000000000..4f6b3d329b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int64x2x2_t
+f_vld2q_lane_s64 (int64_t * p, int64x2x2_t v)
+{
+  int64x2x2_t res;
+  res = vld2q_lane_s64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld2q_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c
new file mode 100644
index 00000000000..889435bffe0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int8x16x2_t
+f_vld2q_lane_s8 (int8_t * p, int8x16x2_t v)
+{
+  int8x16x2_t res;
+  res = vld2q_lane_s8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld2q_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c
new file mode 100644
index 00000000000..cf5ff434918
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint16x8x2_t
+f_vld2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
+{
+  uint16x8x2_t res;
+  res = vld2q_lane_u16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld2q_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c
new file mode 100644
index 00000000000..eab1cfb302f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint32x4x2_t
+f_vld2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
+{
+  uint32x4x2_t res;
+  res = vld2q_lane_u32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld2q_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c
new file mode 100644
index 00000000000..f2db54ed515
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint64x2x2_t
+f_vld2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
+{
+  uint64x2x2_t res;
+  res = vld2q_lane_u64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld2q_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c
new file mode 100644
index 00000000000..33a2ce36b98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint8x16x2_t
+f_vld2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
+{
+  uint8x16x2_t res;
+  res = vld2q_lane_u8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld2q_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c
new file mode 100644
index 00000000000..88a4e7710a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float32x2x3_t
+f_vld3_lane_f32 (float32_t * p, float32x2x3_t v)
+{
+  float32x2x3_t res;
+  res = vld3_lane_f32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld3_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c
new file mode 100644
index 00000000000..eabb865f655
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float64x1x3_t
+f_vld3_lane_f64 (float64_t * p, float64x1x3_t v)
+{
+  float64x1x3_t res;
+  res = vld3_lane_f64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld3_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c
new file mode 100644
index 00000000000..e0e3350c222
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+poly8x8x3_t
+f_vld3_lane_p8 (poly8_t * p, poly8x8x3_t v)
+{
+  poly8x8x3_t res;
+  res = vld3_lane_p8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld3_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c
new file mode 100644
index 00000000000..693c99b0853
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int16x4x3_t
+f_vld3_lane_s16 (int16_t * p, int16x4x3_t v)
+{
+  int16x4x3_t res;
+  res = vld3_lane_s16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld3_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c
new file mode 100644
index 00000000000..44d0e337c88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int32x2x3_t
+f_vld3_lane_s32 (int32_t * p, int32x2x3_t v)
+{
+  int32x2x3_t res;
+  res = vld3_lane_s32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld3_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c
new file mode 100644
index 00000000000..eb2daf21c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int64x1x3_t
+f_vld3_lane_s64 (int64_t * p, int64x1x3_t v)
+{
+  int64x1x3_t res;
+  res = vld3_lane_s64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld3_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c
new file mode 100644
index 00000000000..3c2efe96072
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int8x8x3_t
+f_vld3_lane_s8 (int8_t * p, int8x8x3_t v)
+{
+  int8x8x3_t res;
+  res = vld3_lane_s8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld3_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c
new file mode 100644
index 00000000000..eafeefe8a24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint16x4x3_t
+f_vld3_lane_u16 (uint16_t * p, uint16x4x3_t v)
+{
+  uint16x4x3_t res;
+  res = vld3_lane_u16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld3_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c
new file mode 100644
index 00000000000..2e5f029ac9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint32x2x3_t
+f_vld3_lane_u32 (uint32_t * p, uint32x2x3_t v)
+{
+  uint32x2x3_t res;
+  res = vld3_lane_u32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld3_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c
new file mode 100644
index 00000000000..8a164735053
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint64x1x3_t
+f_vld3_lane_u64 (uint64_t * p, uint64x1x3_t v)
+{
+  uint64x1x3_t res;
+  res = vld3_lane_u64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld3_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c
new file mode 100644
index 00000000000..6cc821472fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint8x8x3_t
+f_vld3_lane_u8 (uint8_t * p, uint8x8x3_t v)
+{
+  uint8x8x3_t res;
+  res = vld3_lane_u8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld3_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c
new file mode 100644
index 00000000000..50c9f444bfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float32x4x3_t
+f_vld3q_lane_f32 (float32_t * p, float32x4x3_t v)
+{
+  float32x4x3_t res;
+  res = vld3q_lane_f32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld3q_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c
new file mode 100644
index 00000000000..a516ce76c1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float64x2x3_t
+f_vld3q_lane_f64 (float64_t * p, float64x2x3_t v)
+{
+  float64x2x3_t res;
+  res = vld3q_lane_f64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld3q_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c
new file mode 100644
index 00000000000..93aa7840091
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+poly8x16x3_t
+f_vld3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
+{
+  poly8x16x3_t res;
+  res = vld3q_lane_p8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld3q_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c
new file mode 100644
index 00000000000..6e570ec6a48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int16x8x3_t
+f_vld3q_lane_s16 (int16_t * p, int16x8x3_t v)
+{
+  int16x8x3_t res;
+  res = vld3q_lane_s16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld3q_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c
new file mode 100644
index 00000000000..f7e58da2949
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int32x4x3_t
+f_vld3q_lane_s32 (int32_t * p, int32x4x3_t v)
+{
+  int32x4x3_t res;
+  res = vld3q_lane_s32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld3q_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c
new file mode 100644
index 00000000000..9d6bb50da76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int64x2x3_t
+f_vld3q_lane_s64 (int64_t * p, int64x2x3_t v)
+{
+  int64x2x3_t res;
+  res = vld3q_lane_s64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld3q_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c
new file mode 100644
index 00000000000..a450c17debd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int8x16x3_t
+f_vld3q_lane_s8 (int8_t * p, int8x16x3_t v)
+{
+  int8x16x3_t res;
+  res = vld3q_lane_s8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld3q_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c
new file mode 100644
index 00000000000..459a5175bbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint16x8x3_t
+f_vld3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
+{
+  uint16x8x3_t res;
+  res = vld3q_lane_u16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld3q_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c
new file mode 100644
index 00000000000..2657553b42d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint32x4x3_t
+f_vld3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
+{
+  uint32x4x3_t res;
+  res = vld3q_lane_u32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld3q_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c
new file mode 100644
index 00000000000..92e717b0a71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint64x2x3_t
+f_vld3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
+{
+  uint64x2x3_t res;
+  res = vld3q_lane_u64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld3q_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c
new file mode 100644
index 00000000000..273543c7daa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint8x16x3_t
+f_vld3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
+{
+  uint8x16x3_t res;
+  res = vld3q_lane_u8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld3q_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c
new file mode 100644
index 00000000000..38a458f797e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float32x2x4_t
+f_vld4_lane_f32 (float32_t * p, float32x2x4_t v)
+{
+  float32x2x4_t res;
+  res = vld4_lane_f32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld4_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c
new file mode 100644
index 00000000000..b0ca390fb00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float64x1x4_t
+f_vld4_lane_f64 (float64_t * p, float64x1x4_t v)
+{
+  float64x1x4_t res;
+  res = vld4_lane_f64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld4_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c
new file mode 100644
index 00000000000..864598bbc6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+poly8x8x4_t
+f_vld4_lane_p8 (poly8_t * p, poly8x8x4_t v)
+{
+  poly8x8x4_t res;
+  res = vld4_lane_p8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld4_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c
new file mode 100644
index 00000000000..ef545fe269c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int16x4x4_t
+f_vld4_lane_s16 (int16_t * p, int16x4x4_t v)
+{
+  int16x4x4_t res;
+  res = vld4_lane_s16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld4_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c
new file mode 100644
index 00000000000..60d8a623414
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int32x2x4_t
+f_vld4_lane_s32 (int32_t * p, int32x2x4_t v)
+{
+  int32x2x4_t res;
+  res = vld4_lane_s32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld4_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c
new file mode 100644
index 00000000000..5f12dcd2055
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int64x1x4_t
+f_vld4_lane_s64 (int64_t * p, int64x1x4_t v)
+{
+  int64x1x4_t res;
+  res = vld4_lane_s64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld4_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c
new file mode 100644
index 00000000000..39c8ec71fa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int8x8x4_t
+f_vld4_lane_s8 (int8_t * p, int8x8x4_t v)
+{
+  int8x8x4_t res;
+  res = vld4_lane_s8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld4_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c
new file mode 100644
index 00000000000..d1c2984f54e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint16x4x4_t
+f_vld4_lane_u16 (uint16_t * p, uint16x4x4_t v)
+{
+  uint16x4x4_t res;
+  res = vld4_lane_u16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld4_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c
new file mode 100644
index 00000000000..55d002da6dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint32x2x4_t
+f_vld4_lane_u32 (uint32_t * p, uint32x2x4_t v)
+{
+  uint32x2x4_t res;
+  res = vld4_lane_u32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld4_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c
new file mode 100644
index 00000000000..e5d05a6668b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint64x1x4_t
+f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v)
+{
+  uint64x1x4_t res;
+  res = vld4_lane_u64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vld4_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c
new file mode 100644
index 00000000000..76975e2da04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint8x8x4_t
+f_vld4_lane_u8 (uint8_t * p, uint8x8x4_t v)
+{
+  uint8x8x4_t res;
+  res = vld4_lane_u8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld4_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c
new file mode 100644
index 00000000000..695f0c5ba7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float32x4x4_t
+f_vld4q_lane_f32 (float32_t * p, float32x4x4_t v)
+{
+  float32x4x4_t res;
+  res = vld4q_lane_f32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld4q_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c
new file mode 100644
index 00000000000..c92f99d55aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+float64x2x4_t
+f_vld4q_lane_f64 (float64_t * p, float64x2x4_t v)
+{
+  float64x2x4_t res;
+  res = vld4q_lane_f64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld4q_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c
new file mode 100644
index 00000000000..10430be6ea9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+poly8x16x4_t
+f_vld4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
+{
+  poly8x16x4_t res;
+  res = vld4q_lane_p8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld4q_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c
new file mode 100644
index 00000000000..a75e659d28f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int16x8x4_t
+f_vld4q_lane_s16 (int16_t * p, int16x8x4_t v)
+{
+  int16x8x4_t res;
+  res = vld4q_lane_s16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld4q_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c
new file mode 100644
index 00000000000..90c92e69eaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int32x4x4_t
+f_vld4q_lane_s32 (int32_t * p, int32x4x4_t v)
+{
+  int32x4x4_t res;
+  res = vld4q_lane_s32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld4q_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c
new file mode 100644
index 00000000000..408829cde79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int64x2x4_t
+f_vld4q_lane_s64 (int64_t * p, int64x2x4_t v)
+{
+  int64x2x4_t res;
+  res = vld4q_lane_s64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld4q_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c
new file mode 100644
index 00000000000..6720becb02a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+int8x16x4_t
+f_vld4q_lane_s8 (int8_t * p, int8x16x4_t v)
+{
+  int8x16x4_t res;
+  res = vld4q_lane_s8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld4q_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c
new file mode 100644
index 00000000000..a98c34787b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint16x8x4_t
+f_vld4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
+{
+  uint16x8x4_t res;
+  res = vld4q_lane_u16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  res = vld4q_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c
new file mode 100644
index 00000000000..d006309c4f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint32x4x4_t
+f_vld4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
+{
+  uint32x4x4_t res;
+  res = vld4q_lane_u32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  res = vld4q_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c
new file mode 100644
index 00000000000..350225ebbdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint64x2x4_t
+f_vld4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
+{
+  uint64x2x4_t res;
+  res = vld4q_lane_u64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vld4q_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c
new file mode 100644
index 00000000000..44637bf693f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+uint8x16x4_t
+f_vld4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
+{
+  uint8x16x4_t res;
+  res = vld4q_lane_u8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  res = vld4q_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c
new file mode 100644
index 00000000000..7a8abb1e1fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_f32 (float32_t * p, float32x2x2_t v)
+{
+  vst2_lane_f32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst2_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c
new file mode 100644
index 00000000000..a7edae2aeb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_f64 (float64_t * p, float64x1x2_t v)
+{
+  vst2_lane_f64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst2_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c
new file mode 100644
index 00000000000..4e6af79b044
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_p8 (poly8_t * p, poly8x8x2_t v)
+{
+  vst2_lane_p8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst2_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c
new file mode 100644
index 00000000000..e6b9be348ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_s16 (int16_t * p, int16x4x2_t v)
+{
+  vst2_lane_s16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst2_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c
new file mode 100644
index 00000000000..03c4cb0813c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_s32 (int32_t * p, int32x2x2_t v)
+{
+  vst2_lane_s32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst2_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c
new file mode 100644
index 00000000000..9f49ced2d2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_s64 (int64_t * p, int64x1x2_t v)
+{
+  vst2_lane_s64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst2_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c
new file mode 100644
index 00000000000..74f7ce491be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_s8 (int8_t * p, int8x8x2_t v)
+{
+  vst2_lane_s8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst2_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c
new file mode 100644
index 00000000000..0d1fd7c5f54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_u16 (uint16_t * p, uint16x4x2_t v)
+{
+  vst2_lane_u16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst2_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c
new file mode 100644
index 00000000000..eb5482e0971
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_u32 (uint32_t * p, uint32x2x2_t v)
+{
+  vst2_lane_u32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst2_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c
new file mode 100644
index 00000000000..36d37830d3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_u64 (uint64_t * p, uint64x1x2_t v)
+{
+  vst2_lane_u64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst2_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c
new file mode 100644
index 00000000000..1de064a5778
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2_lane_u8 (uint8_t * p, uint8x8x2_t v)
+{
+  vst2_lane_u8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst2_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c
new file mode 100644
index 00000000000..d0b25f19509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_f32 (float32_t * p, float32x4x2_t v)
+{
+  vst2q_lane_f32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst2q_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c
new file mode 100644
index 00000000000..af34ae7121e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_f64 (float64_t * p, float64x2x2_t v)
+{
+  vst2q_lane_f64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst2q_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c
new file mode 100644
index 00000000000..89bd1b85b7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
+{
+  vst2q_lane_p8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst2q_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c
new file mode 100644
index 00000000000..fe67496b695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_s16 (int16_t * p, int16x8x2_t v)
+{
+  vst2q_lane_s16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst2q_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c
new file mode 100644
index 00000000000..e60a4a8a0b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_s32 (int32_t * p, int32x4x2_t v)
+{
+  vst2q_lane_s32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst2q_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c
new file mode 100644
index 00000000000..4bcdc8b6377
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_s64 (int64_t * p, int64x2x2_t v)
+{
+  vst2q_lane_s64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst2q_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c
new file mode 100644
index 00000000000..78b5e69149e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_s8 (int8_t * p, int8x16x2_t v)
+{
+  vst2q_lane_s8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst2q_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c
new file mode 100644
index 00000000000..025d83db5e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
+{
+  vst2q_lane_u16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst2q_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c
new file mode 100644
index 00000000000..54a0c108cca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
+{
+  vst2q_lane_u32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst2q_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c
new file mode 100644
index 00000000000..2d2cb533ec2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
+{
+  vst2q_lane_u64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst2q_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c
new file mode 100644
index 00000000000..9172e001803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
+{
+  vst2q_lane_u8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst2q_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c
new file mode 100644
index 00000000000..f5b016734a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_f32 (float32_t * p, float32x2x3_t v)
+{
+  vst3_lane_f32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst3_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c
new file mode 100644
index 00000000000..e7607e7e310
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_f64 (float64_t * p, float64x1x3_t v)
+{
+  vst3_lane_f64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst3_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c
new file mode 100644
index 00000000000..aebcc76ec58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_p8 (poly8_t * p, poly8x8x3_t v)
+{
+  vst3_lane_p8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst3_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c
new file mode 100644
index 00000000000..abd2496e4a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_s16 (int16_t * p, int16x4x3_t v)
+{
+  vst3_lane_s16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst3_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c
new file mode 100644
index 00000000000..5f810c39546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_s32 (int32_t * p, int32x2x3_t v)
+{
+  vst3_lane_s32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst3_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c
new file mode 100644
index 00000000000..c76ac6e558a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_s64 (int64_t * p, int64x1x3_t v)
+{
+  vst3_lane_s64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst3_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c
new file mode 100644
index 00000000000..3e1d75705ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_s8 (int8_t * p, int8x8x3_t v)
+{
+  vst3_lane_s8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst3_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c
new file mode 100644
index 00000000000..c58bd70a610
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_u16 (uint16_t * p, uint16x4x3_t v)
+{
+  vst3_lane_u16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst3_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c
new file mode 100644
index 00000000000..9e53e204560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_u32 (uint32_t * p, uint32x2x3_t v)
+{
+  vst3_lane_u32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst3_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c
new file mode 100644
index 00000000000..c1c4aa19cf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_u64 (uint64_t * p, uint64x1x3_t v)
+{
+  vst3_lane_u64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst3_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c
new file mode 100644
index 00000000000..ff8af48e115
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3_lane_u8 (uint8_t * p, uint8x8x3_t v)
+{
+  vst3_lane_u8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst3_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c
new file mode 100644
index 00000000000..a98a9a0c85f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_f32 (float32_t * p, float32x4x3_t v)
+{
+  vst3q_lane_f32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst3q_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c
new file mode 100644
index 00000000000..0281c11771b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_f64 (float64_t * p, float64x2x3_t v)
+{
+  vst3q_lane_f64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst3q_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c
new file mode 100644
index 00000000000..75d666cb646
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
+{
+  vst3q_lane_p8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst3q_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c
new file mode 100644
index 00000000000..3c85372547c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_s16 (int16_t * p, int16x8x3_t v)
+{
+  vst3q_lane_s16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst3q_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c
new file mode 100644
index 00000000000..9afdee63231
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_s32 (int32_t * p, int32x4x3_t v)
+{
+  vst3q_lane_s32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst3q_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c
new file mode 100644
index 00000000000..e089afec5b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_s64 (int64_t * p, int64x2x3_t v)
+{
+  vst3q_lane_s64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst3q_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c
new file mode 100644
index 00000000000..b6584ab432c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_s8 (int8_t * p, int8x16x3_t v)
+{
+  vst3q_lane_s8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst3q_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c
new file mode 100644
index 00000000000..9985054606b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
+{
+  vst3q_lane_u16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst3q_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c
new file mode 100644
index 00000000000..34f3b379264
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
+{
+  vst3q_lane_u32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst3q_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c
new file mode 100644
index 00000000000..5428d3c19e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
+{
+  vst3q_lane_u64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst3q_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c
new file mode 100644
index 00000000000..f7fd73b1829
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
+{
+  vst3q_lane_u8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst3q_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c
new file mode 100644
index 00000000000..29ca2a2dbbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_f32 (float32_t * p, float32x2x4_t v)
+{
+  vst4_lane_f32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst4_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c
new file mode 100644
index 00000000000..efe230d354e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_f64 (float64_t * p, float64x1x4_t v)
+{
+  vst4_lane_f64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst4_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c
new file mode 100644
index 00000000000..6a5474b5f73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_p8 (poly8_t * p, poly8x8x4_t v)
+{
+  vst4_lane_p8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst4_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c
new file mode 100644
index 00000000000..c20bcc9a2f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_s16 (int16_t * p, int16x4x4_t v)
+{
+  vst4_lane_s16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst4_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c
new file mode 100644
index 00000000000..9aafe70fe58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_s32 (int32_t * p, int32x2x4_t v)
+{
+  vst4_lane_s32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst4_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c
new file mode 100644
index 00000000000..0db8285b12a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_s64 (int64_t * p, int64x1x4_t v)
+{
+  vst4_lane_s64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst4_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c
new file mode 100644
index 00000000000..5a70a208444
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_s8 (int8_t * p, int8x8x4_t v)
+{
+  vst4_lane_s8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst4_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c
new file mode 100644
index 00000000000..60114cb8e94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_u16 (uint16_t * p, uint16x4x4_t v)
+{
+  vst4_lane_u16 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst4_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c
new file mode 100644
index 00000000000..2e41441573b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_u32 (uint32_t * p, uint32x2x4_t v)
+{
+  vst4_lane_u32 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst4_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c
new file mode 100644
index 00000000000..d90844bb091
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_u64 (uint64_t * p, uint64x1x4_t v)
+{
+  vst4_lane_u64 (p, v, 1); /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  vst4_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c
new file mode 100644
index 00000000000..6d838668074
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4_lane_u8 (uint8_t * p, uint8x8x4_t v)
+{
+  vst4_lane_u8 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst4_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c
new file mode 100644
index 00000000000..35a10d6af14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_f32 (float32_t * p, float32x4x4_t v)
+{
+  vst4q_lane_f32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst4q_lane_f32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c
new file mode 100644
index 00000000000..6e202e16a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_f64 (float64_t * p, float64x2x4_t v)
+{
+  vst4q_lane_f64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst4q_lane_f64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c
new file mode 100644
index 00000000000..b4702749065
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
+{
+  vst4q_lane_p8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst4q_lane_p8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c
new file mode 100644
index 00000000000..bbece00caac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_s16 (int16_t * p, int16x8x4_t v)
+{
+  vst4q_lane_s16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst4q_lane_s16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c
new file mode 100644
index 00000000000..eaa3d0025f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_s32 (int32_t * p, int32x4x4_t v)
+{
+  vst4q_lane_s32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst4q_lane_s32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c
new file mode 100644
index 00000000000..0b122619d02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_s64 (int64_t * p, int64x2x4_t v)
+{
+  vst4q_lane_s64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst4q_lane_s64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c
new file mode 100644
index 00000000000..d3444222bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_s8 (int8_t * p, int8x16x4_t v)
+{
+  vst4q_lane_s8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst4q_lane_s8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c
new file mode 100644
index 00000000000..d74787f89d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
+{
+  vst4q_lane_u16 (p, v, 8); /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
+  vst4q_lane_u16 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c
new file mode 100644
index 00000000000..c85ce7ccd18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
+{
+  vst4q_lane_u32 (p, v, 4); /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
+  vst4q_lane_u32 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c
new file mode 100644
index 00000000000..84134af1ac9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
+{
+  vst4q_lane_u64 (p, v, 2); /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  vst4q_lane_u64 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  return;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c
new file mode 100644
index 00000000000..0ff9093cb63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c
@@ -0,0 +1,10 @@
+#include <arm_neon.h>
+
+
+void
+f_vst4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
+{
+  vst4q_lane_u8 (p, v, 16); /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
+  vst4q_lane_u8 (p, v, -1); /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
+  return;
+}