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authorjoseph <joseph@7b3dc134-2b1b-0410-93df-9e9f96275f8d>2006-12-07 18:33:12 +0000
committerjoseph <joseph@7b3dc134-2b1b-0410-93df-9e9f96275f8d>2006-12-07 18:33:12 +0000
commit93358c6f7bdae8f05ece835c085718857da7ad7d (patch)
treec53e105586cb3e35ac372409fce794c428be4013 /libc
parentb1c243824ff52877c270658e9c66083930e78ac8 (diff)
libc:
* misc/tst-efgcvt.c (ecvt_tests): Disable subnormal test for E500 double. * sysdeps/powerpc/bits/fenv.h: Include E500 definitions. Based on SPE add-on by Aldy Hernandez. * sysdeps/powerpc/fpu/bits/fenvinline.h: Change _SOFT_FLOAT to __NO_FPRS__. * sysdeps/powerpc/fpu/bits/mathinline.h: Likewise. * sysdeps/powerpc/fpu/fpu_control.h: Include soft-float and E500 definitions. Based on SPE add-on by Aldy Hernandez. * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S: If __CONTEXT_EXTRA defined, include <getcontext-extra.S>. * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S: If __CONTEXT_EXTRA defined, include <setcontext-extra.S>. * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S: If __CONTEXT_EXTRA defined, include <getcontext-extra.S> and <setcontext-extra.S>. ports: Add PowerPC E500 port, based on SPE add-on by Aldy Hernandez. * sysdeps/powerpc/preconfigure: New. * sysdeps/powerpc/powerpc32/e500: New. * sysdeps/unix/sysv/linux/powerpc/powerpc32/e500: New. git-svn-id: svn://svn.eglibc.org/trunk@877 7b3dc134-2b1b-0410-93df-9e9f96275f8d
Diffstat (limited to 'libc')
-rw-r--r--libc/ChangeLog.eglibc19
-rw-r--r--libc/misc/tst-efgcvt.c2
-rw-r--r--libc/sysdeps/powerpc/bits/fenv.h64
-rw-r--r--libc/sysdeps/powerpc/fpu/bits/fenvinline.h4
-rw-r--r--libc/sysdeps/powerpc/fpu/bits/mathinline.h4
-rw-r--r--libc/sysdeps/powerpc/fpu/fpu_control.h55
-rw-r--r--libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S5
-rw-r--r--libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S4
-rw-r--r--libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S8
9 files changed, 158 insertions, 7 deletions
diff --git a/libc/ChangeLog.eglibc b/libc/ChangeLog.eglibc
index b2e00a581..277fbea48 100644
--- a/libc/ChangeLog.eglibc
+++ b/libc/ChangeLog.eglibc
@@ -1,3 +1,22 @@
+2006-12-07 Joseph Myers <joseph@codesourcery.com>
+
+ * misc/tst-efgcvt.c (ecvt_tests): Disable subnormal test for E500
+ double.
+ * sysdeps/powerpc/bits/fenv.h: Include E500 definitions. Based on
+ SPE add-on by Aldy Hernandez.
+ * sysdeps/powerpc/fpu/bits/fenvinline.h: Change _SOFT_FLOAT to
+ __NO_FPRS__.
+ * sysdeps/powerpc/fpu/bits/mathinline.h: Likewise.
+ * sysdeps/powerpc/fpu/fpu_control.h: Include soft-float and E500
+ definitions. Based on SPE add-on by Aldy Hernandez.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S:
+ If __CONTEXT_EXTRA defined, include <getcontext-extra.S>.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S:
+ If __CONTEXT_EXTRA defined, include <setcontext-extra.S>.
+ * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S:
+ If __CONTEXT_EXTRA defined, include <getcontext-extra.S> and
+ <setcontext-extra.S>.
+
2006-11-13 Joseph S. Myers <joseph@codesourcery.com>
* sysdeps/alpha/bits/mathdef.h (float_t): Always define as float.
diff --git a/libc/misc/tst-efgcvt.c b/libc/misc/tst-efgcvt.c
index 30ab0f17a..632015aed 100644
--- a/libc/misc/tst-efgcvt.c
+++ b/libc/misc/tst-efgcvt.c
@@ -60,7 +60,7 @@ static testcase ecvt_tests[] =
{ 123.01, -4, 3, "" },
{ 126.71, -4, 3, "" },
{ 0.0, 4, 1, "0000" },
-#if DBL_MANT_DIG == 53
+#if DBL_MANT_DIG == 53 && !(defined __powerpc__ && defined __NO_FPRS__ && !defined _SOFT_FLOAT && !defined _SOFT_DOUBLE)
{ 0x1p-1074, 3, -323, "494" },
{ -0x1p-1074, 3, -323, "494" },
#endif
diff --git a/libc/sysdeps/powerpc/bits/fenv.h b/libc/sysdeps/powerpc/bits/fenv.h
index 8509b4b0c..60d1a0d36 100644
--- a/libc/sysdeps/powerpc/bits/fenv.h
+++ b/libc/sysdeps/powerpc/bits/fenv.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
+/* Copyright (C) 1997, 1998, 1999, 2004, 2006 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -20,6 +20,66 @@
# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
#endif
+#if defined __NO_FPRS__ && !defined _SOFT_FLOAT /* E500 */
+
+/* Define bits representing the exception. We use the bit positions of
+ the appropriate bits in the SPEFSCR... */
+enum
+ {
+ FE_INEXACT = 1 << (63 - 42),
+#define FE_INEXACT FE_INEXACT
+ FE_INVALID = 1 << (63 - 43),
+#define FE_INVALID FE_INVALID
+ FE_DIVBYZERO = 1 << (63 - 44),
+#define FE_DIVBYZERO FE_DIVBYZERO
+ FE_UNDERFLOW = 1 << (63 - 45),
+#define FE_UNDERFLOW FE_UNDERFLOW
+ FE_OVERFLOW = 1 << (63 - 46)
+#define FE_OVERFLOW FE_OVERFLOW
+ };
+
+#define FE_ALL_EXCEPT \
+ (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
+
+/* The E500 support all of the four defined rounding modes. We use
+ the bit pattern in the SPEFSCR as the values for the appropriate
+ macros. */
+enum
+ {
+ FE_TONEAREST = 0,
+#define FE_TONEAREST FE_TONEAREST
+ FE_TOWARDZERO = 1,
+#define FE_TOWARDZERO FE_TOWARDZERO
+ FE_UPWARD = 2,
+#define FE_UPWARD FE_UPWARD
+ FE_DOWNWARD = 3
+#define FE_DOWNWARD FE_DOWNWARD
+ };
+
+/* Type representing exception flags. */
+typedef unsigned int fexcept_t;
+
+typedef double fenv_t;
+
+/* If the default argument is used we use this value. */
+extern const fenv_t __fe_dfl_env;
+#define FE_DFL_ENV (&__fe_dfl_env)
+
+#ifdef __USE_GNU
+/* Floating-point environment where all exceptions are enabled. Note that
+ this is not sufficient to give you SIGFPE. */
+extern const fenv_t __fe_enabled_env;
+# define FE_ENABLED_ENV (&__fe_enabled_env)
+
+/* Floating-point environment with all exceptions enabled. Note that
+ just evaluating this value will set the processor into 'FPU
+ exceptions imprecise recoverable' mode, which may cause a significant
+ performance penalty (but have no other visible effect). */
+extern const fenv_t *__fe_nomask_env (void);
+# define FE_NOMASK_ENV (__fe_nomask_env ())
+#endif
+
+#else /* PowerPC 6xx floating-point. */
/* Define bits representing the exception. We use the bit positions of
the appropriate bits in the FPSCR... */
@@ -143,3 +203,5 @@ extern const fenv_t __fe_nonieee_env;
extern const fenv_t *__fe_nomask_env (void);
# define FE_NOMASK_ENV (__fe_nomask_env ())
#endif
+
+#endif
diff --git a/libc/sysdeps/powerpc/fpu/bits/fenvinline.h b/libc/sysdeps/powerpc/fpu/bits/fenvinline.h
index f7700a49e..7e632933e 100644
--- a/libc/sysdeps/powerpc/fpu/bits/fenvinline.h
+++ b/libc/sysdeps/powerpc/fpu/bits/fenvinline.h
@@ -18,7 +18,7 @@
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
-#if defined __GNUC__ && !defined _SOFT_FLOAT && !defined __NO_MATH_INLINES
+#if defined __GNUC__ && !defined __NO_FPRS__ && !defined __NO_MATH_INLINES
/* Inline definition for fegetround. */
# define fegetround() \
@@ -58,4 +58,4 @@
: 0) \
: (feclearexcept) (__excepts))
-#endif /* __GNUC__ && !_SOFT_FLOAT */
+#endif /* __GNUC__ && !__NO_FPRS__ */
diff --git a/libc/sysdeps/powerpc/fpu/bits/mathinline.h b/libc/sysdeps/powerpc/fpu/bits/mathinline.h
index 04478309d..ddc296d0d 100644
--- a/libc/sysdeps/powerpc/fpu/bits/mathinline.h
+++ b/libc/sysdeps/powerpc/fpu/bits/mathinline.h
@@ -28,7 +28,7 @@
# define __MATH_INLINE extern __inline
#endif /* __cplusplus */
-#if defined __GNUC__ && !defined _SOFT_FLOAT
+#if defined __GNUC__ && !defined __NO_FPRS__
#ifdef __USE_ISOC99
# if !__GNUC_PREREQ (2,97)
@@ -121,4 +121,4 @@ __NTH (fdimf (float __x, float __y))
#endif /* __USE_ISOC99 */
#endif /* !__NO_MATH_INLINES && __OPTIMIZE__ */
-#endif /* __GNUC__ && !_SOFT_FLOAT */
+#endif /* __GNUC__ && !__NO_FPRS__ */
diff --git a/libc/sysdeps/powerpc/fpu/fpu_control.h b/libc/sysdeps/powerpc/fpu/fpu_control.h
index 1b2ba87c9..2e420bfa6 100644
--- a/libc/sysdeps/powerpc/fpu/fpu_control.h
+++ b/libc/sysdeps/powerpc/fpu/fpu_control.h
@@ -1,5 +1,5 @@
/* FPU control word definitions. PowerPC version.
- Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998, 2004, 2006 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -20,6 +20,57 @@
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H
+#ifdef _SOFT_FLOAT
+
+#define _FPU_RESERVED 0xffffffff
+#define _FPU_DEFAULT 0x00000000 /* Default value. */
+typedef unsigned int fpu_control_t;
+#define _FPU_GETCW(cw) 0
+#define _FPU_SETCW(cw) do { } while (0)
+extern fpu_control_t __fpu_control;
+
+#elif defined __NO_FPRS__ /* E500 */
+
+/* rounding control */
+#define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
+#define _FPU_RC_DOWN 0x03
+#define _FPU_RC_UP 0x02
+#define _FPU_RC_ZERO 0x01
+
+/* masking of interrupts */
+#define _FPU_MASK_ZM 0x10 /* zero divide */
+#define _FPU_MASK_OM 0x40 /* overflow */
+#define _FPU_MASK_UM 0x80 /* underflow */
+#define _FPU_MASK_XM 0x40 /* inexact */
+#define _FPU_MASK_IM 0x20 /* invalid operation */
+
+#define _FPU_RESERVED 0xff3fff7f /* These bits are reserved are not changed. */
+
+/* The fdlibm code requires no interrupts for exceptions. */
+#define _FPU_DEFAULT 0x00000000 /* Default value. */
+
+/* IEEE: same as above, but (some) exceptions;
+ we leave the 'inexact' exception off.
+ */
+#define _FPU_IEEE 0x000003c0
+
+/* Type of the control word. */
+typedef unsigned int fpu_control_t;
+
+/* Macros for accessing the hardware control word. */
+#define _FPU_GETCW(__cw) ({ \
+ unsigned int env; \
+ asm volatile ("mfspefscr %0" : "=r" (env)); \
+ (__cw) = env; })
+#define _FPU_SETCW(__cw) ({ \
+ unsigned int env = __cw; \
+ asm volatile ("mtspefscr %0" : : "r" (env)); })
+
+/* Default control word set at startup. */
+extern fpu_control_t __fpu_control;
+
+#else /* PowerPC 6xx floating-point. */
+
/* rounding control */
#define _FPU_RC_NEAREST 0x00 /* RECOMMENDED */
#define _FPU_RC_DOWN 0x03
@@ -66,4 +117,6 @@ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
+#endif
+
#endif /* _FPU_CONTROL_H */
diff --git a/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S b/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
index c28c34664..bad479998 100644
--- a/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
+++ b/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S
@@ -267,6 +267,11 @@ ENTRY(__CONTEXT_FUNC_NAME)
2: /* L(no_vec): */
# endif
#endif
+
+#ifdef __CONTEXT_EXTRA
+#include <getcontext-extra.S>
+#endif
+
/* We need to set up parms and call sigprocmask which will clobber
volatile registers. So before the call we need to retrieve the
original ucontext ptr (parm1) from stack and store the UC_REGS_PTR
diff --git a/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S b/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
index 40a7a24f1..c98a4190d 100644
--- a/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
+++ b/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
@@ -233,6 +233,10 @@ ENTRY(__CONTEXT_FUNC_NAME)
lfd fp31,_UC_FREGS+(31*8)(r31)
#endif /* __CONTEXT_ENABLE_FPRS */
+#ifdef __CONTEXT_EXTRA
+#include <setcontext-extra.S>
+#endif
+
/* Restore LR and CCR, and set CTR to the NIP value */
lwz r3,_UC_GREGS+(PT_LNK*4)(r31)
lwz r4,_UC_GREGS+(PT_NIP*4)(r31)
diff --git a/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S b/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
index 0c7b945ed..d5e1f2c7d 100644
--- a/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
+++ b/libc/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
@@ -270,6 +270,10 @@ ENTRY(__CONTEXT_FUNC_NAME)
# endif /* __CONTEXT_ENABLE_VRS */
#endif /* __CONTEXT_ENABLE_FPRS */
+#ifdef __CONTEXT_EXTRA
+#include <getcontext-extra.S>
+#endif
+
/* Restore ucontext (parm1) from stack. */
lwz r12,_FRAME_PARM_SAVE1(r1)
li r4,0
@@ -459,6 +463,10 @@ ENTRY(__CONTEXT_FUNC_NAME)
lfd fp31,_UC_FREGS+(31*8)(r31)
#endif /* __CONTEXT_ENABLE_FPRS */
+#ifdef __CONTEXT_EXTRA
+#include <setcontext-extra.S>
+#endif
+
/* Restore LR and CCR, and set CTR to the NIP value */
lwz r3,_UC_GREGS+(PT_LNK*4)(r31)
lwz r4,_UC_GREGS+(PT_NIP*4)(r31)