ci/qemu.git - [no description]

Age	Commit message (Expand)	Author
2022-05-06	target/xtensa: implement cache test option opcodes	Max Filippov
2022-05-06	target/xtensa: use tcg_constant_* for remaining opcodes	Max Filippov
2022-05-06	target/xtensa: use tcg_constant_* for FPU conversion opcodes	Max Filippov
2022-05-06	target/xtensa: use tcg_constant_* for numbered special registers	Max Filippov
2022-05-06	target/xtensa: use tcg_constant_* for TLB opcodes	Max Filippov
2022-05-06	target/xtensa: use tcg_constant_* for exceptions	Max Filippov
2022-05-06	target/xtensa: use tcg_contatnt_* for numeric literals	Max Filippov
2022-05-06	target/xtensa: fix missing tcg_temp_free in gen_window_check	Max Filippov
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson
2022-04-06	Replace TARGET_WORDS_BIGENDIAN	Marc-André Lureau
2022-01-08	exec/memop: Adding signedness to quad definitions	Frédéric Pétrot
2021-10-15	target/xtensa: Drop check for singlestep_enabled	Richard Henderson
2021-09-14	accel/tcg: Add DisasContextBase argument to translator_ld*	Ilya Leoshkevich
2021-07-21	accel/tcg: Remove TranslatorOps.breakpoint_check	Richard Henderson
2021-07-09	target/xtensa: Use translator_use_goto_tb	Richard Henderson
2021-07-09	tcg: Avoid including 'trace-tcg.h' in target translate.c	Philippe Mathieu-Daudé
2021-05-20	target/xtensa: clean up unaligned access	Max Filippov
2021-05-20	target/xtensa: fix access ring in l32ex	Max Filippov
2021-05-20	target/xtensa: don't generate extra EXCP_DEBUG on exception	Max Filippov
2021-05-20	target/xtensa: Make sure that tb->size != 0	Ilya Leoshkevich
2021-03-10	semihosting: Move include/hw/semihosting/ -> include/semihosting/	Philippe Mathieu-Daudé
2020-08-21	target/xtensa: implement FPU division and square root	Max Filippov
2020-08-21	target/xtensa: add DFPU registers and opcodes	Max Filippov
2020-08-21	target/xtensa: don't access BR regfile directly	Max Filippov
2020-08-21	target/xtensa: move FSR/FCR register accessors	Max Filippov
2020-08-21	target/xtensa: rename FPU2000 translators and helpers	Max Filippov
2020-08-21	target/xtensa: support copying registers up to 64 bits wide	Max Filippov
2020-08-21	target/xtensa: add geometry to xtensa_get_regfile_by_name	Max Filippov
2020-08-21	target/xtensa: make opcode properties more dynamic	Max Filippov
2020-06-22	target/xtensa: drop gen_io_end call	Max Filippov
2020-05-17	target/xtensa: fix simcall for newer hardware	Max Filippov
2020-04-30	target/xtensa: work around missing SR definitions	Max Filippov
2020-04-07	target/xtensa: statically allocate xtensa_insnbufs in DisasContext	Max Filippov
2020-04-07	target/xtensa: fix pasto in pfwait.r opcode name	Max Filippov
2020-04-07	target/xtensa: add FIXME for translation memory leak	Alex Bennée
2020-01-15	tcg: Search includes from the project root source directory	Philippe Mathieu-Daudé
2020-01-06	target/xtensa: fix ps.ring use in MPU configs	Max Filippov
2019-10-28	target/xtensa: fetch code with translator_ld	Emilio G. Cota
2019-08-20	icount: remove unnecessary gen_io_end calls	Pavel Dovgalyuk
2019-08-16	Clean up inclusion of sysemu/sysemu.h	Markus Armbruster
2019-05-28	semihosting: move semihosting configuration into its own directory	Alex Bennée
2019-05-21	Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging	Peter Maydell
2019-05-15	target/xtensa: implement exclusive access option	Max Filippov
2019-05-15	target/xtensa: implement block prefetch option opcodes	Max Filippov
2019-05-14	target/xtensa: implement DIWBUI.P opcode	Max Filippov
2019-05-13	target/xtensa: Use tcg_gen_abs_i32	Richard Henderson
2019-05-10	target/xtensa: implement MPU option	Max Filippov
2019-05-10	target/xtensa: add parity/ECC option SRs	Max Filippov
2019-05-10	target/xtensa: get rid of centralized SR properties	Max Filippov
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson