ci/qemu.git - [no description]

Age	Commit message (Expand)	Author
2022-04-01	target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen	Peter Maydell
2022-03-02	target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()	Wentao_Liang
2022-01-08	exec/memop: Adding signedness to quad definitions	Frédéric Pétrot
2021-12-15	target/arm: Take an exception if PC is misaligned	Richard Henderson
2021-12-15	target/arm: Advance pc for arch single-step exception	Richard Henderson
2021-12-15	target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn	Richard Henderson
2021-10-15	target/arm: Drop checks for singlestep_enabled	Richard Henderson
2021-10-05	tcg: Expand MO_SIZE to 3 bits	Richard Henderson
2021-09-14	accel/tcg: Add DisasContextBase argument to translator_ld*	Ilya Leoshkevich
2021-09-13	target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn	Richard Henderson
2021-09-13	target/arm: Take an exception if PSTATE.IL is set	Peter Maydell
2021-07-21	accel/tcg: Remove TranslatorOps.breakpoint_check	Richard Henderson
2021-07-09	target/arm: Use translator_use_goto_tb for aarch64	Richard Henderson
2021-07-09	tcg: Avoid including 'trace-tcg.h' in target translate.c	Philippe Mathieu-Daudé
2021-07-02	target/arm: Use dup_const() instead of bitfield_replicate()	Peter Maydell
2021-07-02	target/arm: Use asimd_imm_const for A64 decode	Peter Maydell
2021-06-29	target/arm: Improve vector REV	Richard Henderson
2021-06-29	target/arm: Improve REV32	Richard Henderson
2021-06-29	tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64	Richard Henderson
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16	Richard Henderson
2021-06-15	target/arm: Remove fprintf from disas_simd_mod_imm	Richard Henderson
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16	Richard Henderson
2021-06-03	target/arm: Implement bfloat widening fma (indexed)	Richard Henderson
2021-06-03	target/arm: Implement bfloat widening fma (vector)	Richard Henderson
2021-06-03	target/arm: Implement bfloat16 matrix multiply accumulate	Richard Henderson
2021-06-03	target/arm: Implement bfloat16 dot product (indexed)	Richard Henderson
2021-06-03	target/arm: Implement bfloat16 dot product (vector)	Richard Henderson
2021-06-03	target/arm: Implement vector float32 to bfloat16 conversion	Richard Henderson
2021-06-03	target/arm: Implement scalar float32 to bfloat16 conversion	Richard Henderson
2021-06-03	target/arm: Unify unallocated path in disas_fp_1src	Richard Henderson
2021-06-03	target/arm: Mark LDS{MIN,MAX} as signed operations	Richard Henderson
2021-05-25	target/arm: Implement integer matrix multiply accumulate	Richard Henderson
2021-05-25	target/arm: Implement aarch64 SUDOT, USDOT	Richard Henderson
2021-05-25	target/arm: Pass separate addend to FCMLA helpers	Richard Henderson
2021-05-25	target/arm: Pass separate addend to {U, S}DOT helpers	Richard Henderson
2021-05-25	target/arm: Implement SVE2 XAR	Richard Henderson
2021-05-10	target/arm: Share unallocated_encoding() and gen_exception_insn()	Peter Maydell
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (single)	Richard Henderson
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)	Richard Henderson
2021-04-30	target/arm: Use MemOp for size + endian in aa64 vector ld/st	Richard Henderson
2021-04-30	target/arm: Enforce alignment for aa64 load-acq/store-rel	Richard Henderson
2021-04-30	target/arm: Use finalize_memop for aa64 fpr load/store	Richard Henderson
2021-04-30	target/arm: Use finalize_memop for aa64 gpr load/store	Richard Henderson
2021-04-30	target/arm: Add ALIGN_MEM to TBFLAG_ANY	Richard Henderson
2021-04-30	target/arm: Introduce CPUARMTBFlags	Richard Henderson
2021-04-30	target/arm: Add wrapper macros for accessing tbflags	Richard Henderson
2021-04-30	target/arm: Rename TBFLAG_ANY, PSTATE_SS	Richard Henderson
2021-04-30	target/arm: Remove log2_esize parameter to gen_mte_checkN	Richard Henderson
2021-04-30	target/arm: Merge mte_check1, mte_checkN	Richard Henderson
2021-04-30	target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1	Richard Henderson