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-rw-r--r--target/loongarch/cpu.c8
-rw-r--r--target/loongarch/cpu.h18
-rw-r--r--target/loongarch/gdbstub.c43
-rw-r--r--target/loongarch/internals.h3
4 files changed, 58 insertions, 14 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 1c69a76f2b..941e2772bc 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -661,6 +661,11 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
};
#endif
+static gchar *loongarch_gdb_arch_name(CPUState *cs)
+{
+ return g_strdup("loongarch64");
+}
+
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
@@ -683,9 +688,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
cc->disas_set_info = loongarch_cpu_disas_set_info;
- cc->gdb_num_core_regs = 34;
+ cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "loongarch-base64.xml";
cc->gdb_stop_before_watchpoint = true;
+ cc->gdb_arch_name = loongarch_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index a36349df83..dce999aaac 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5)
FIELD(FCSR0, CAUSE, 24, 5)
#define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
-#define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR0, CAUSE, V)
+#define SET_FP_CAUSE(REG, V) \
+ do { \
+ (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
+ } while (0)
+
#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
-#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
+#define SET_FP_ENABLES(REG, V) \
+ do { \
+ (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
+ } while (0)
+
#define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
-#define SET_FP_FLAGS(REG, V) FIELD_DP32(REG, FCSR0, FLAGS, V)
+#define SET_FP_FLAGS(REG, V) \
+ do { \
+ (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
+ } while (0)
+
#define UPDATE_FP_FLAGS(REG, V) \
do { \
(REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 24e126fb2d..a4d1e28e36 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -11,6 +11,24 @@
#include "internals.h"
#include "exec/gdbstub.h"
+uint64_t read_fcc(CPULoongArchState *env)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 8; ++i) {
+ ret |= (uint64_t)env->cf[i] << (i * 8);
+ }
+
+ return ret;
+}
+
+void write_fcc(CPULoongArchState *env, uint64_t val)
+{
+ for (int i = 0; i < 8; ++i) {
+ env->cf[i] = (val >> (i * 8)) & 1;
+ }
+}
+
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
@@ -19,8 +37,11 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
if (0 <= n && n < 32) {
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
- return gdb_get_regl(mem_buf, env->pc);
+ /* orig_a0 */
+ return gdb_get_regl(mem_buf, 0);
} else if (n == 33) {
+ return gdb_get_regl(mem_buf, env->pc);
+ } else if (n == 34) {
return gdb_get_regl(mem_buf, env->CSR_BADV);
}
return 0;
@@ -36,7 +57,7 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (0 <= n && n < 32) {
env->gpr[n] = tmp;
length = sizeof(target_ulong);
- } else if (n == 32) {
+ } else if (n == 33) {
env->pc = tmp;
length = sizeof(target_ulong);
}
@@ -48,9 +69,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,
{
if (0 <= n && n < 32) {
return gdb_get_reg64(mem_buf, env->fpr[n]);
- } else if (32 <= n && n < 40) {
- return gdb_get_reg8(mem_buf, env->cf[n - 32]);
- } else if (n == 40) {
+ } else if (n == 32) {
+ uint64_t val = read_fcc(env);
+ return gdb_get_reg64(mem_buf, val);
+ } else if (n == 33) {
return gdb_get_reg32(mem_buf, env->fcsr0);
}
return 0;
@@ -64,10 +86,11 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
if (0 <= n && n < 32) {
env->fpr[n] = ldq_p(mem_buf);
length = 8;
- } else if (32 <= n && n < 40) {
- env->cf[n - 32] = ldub_p(mem_buf);
- length = 1;
- } else if (n == 40) {
+ } else if (n == 32) {
+ uint64_t val = ldq_p(mem_buf);
+ write_fcc(env, val);
+ length = 8;
+ } else if (n == 33) {
env->fcsr0 = ldl_p(mem_buf);
length = 4;
}
@@ -77,5 +100,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
{
gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
- 41, "loongarch-fpu64.xml", 0);
+ 41, "loongarch-fpu.xml", 0);
}
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index ea227362b6..f01635aed6 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -51,6 +51,9 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
+uint64_t read_fcc(CPULoongArchState *env);
+void write_fcc(CPULoongArchState *env, uint64_t val);
+
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 18:04:57 +0000