diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-05-18 09:26:11 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | bb06941f95edd8a231bee0ac52a8a1dbf6b08e6a (patch) | |
| tree | ec2589c6948061dd7f9ff548e9fdae241dbd2e21 /target/riscv | |
| parent | 96c7fff703d56798bd5dcb1ef6d42ead144580a3 (diff) | |
target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 00a068668f..87e1eddce6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -584,18 +584,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) uint32_t ext = 0; /* Do some ISA extension error checking */ - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && cpu->cfg.ext_d && @@ -610,6 +598,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_ifencei = true; } + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; |