diff options
| author | Atish Patra <atish.patra@wdc.com> | 2022-06-20 16:15:53 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | d3be1299fb37e50535438a675a5b02f5bc068c14 (patch) | |
| tree | ea0a9b6e7a410a980796f9875b448c3c8181d03a /target/riscv | |
| parent | a5a92fd6ef038170231933c60cc2780f52b3a2e1 (diff) | |
target/riscv: pmu: Rename the counters extension to pmu
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 4 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/csr.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05e6521351..1b57b3c439 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -851,7 +851,7 @@ static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); - cpu->cfg.ext_counters = true; + cpu->cfg.ext_pmu = true; cpu->cfg.ext_ifencei = true; cpu->cfg.ext_icsr = true; cpu->cfg.mmu = true; @@ -879,7 +879,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d6397acdf..252c30a55d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -397,7 +397,7 @@ struct RISCVCPUConfig { bool ext_zksed; bool ext_zksh; bool ext_zkt; - bool ext_counters; + bool ext_pmu; bool ext_ifencei; bool ext_icsr; bool ext_svinval; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58d07c511f..0ca05c7788 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -74,8 +74,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno) RISCVCPU *cpu = RISCV_CPU(cs); int ctr_index; - if (!cpu->cfg.ext_counters) { - /* The Counters extensions is not enabled */ + if (!cpu->cfg.ext_pmu) { + /* The PMU extension is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } |