diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-04 23:10:02 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | b97028b8c5a2865bec784bc9b8c4c31ad23a9351 (patch) | |
| tree | 678c9f0734a5d8905d430e5d93945bcd45103cbb /target/riscv | |
| parent | 4e245a9e263e6272c5a47a46c770f3c3965cdf21 (diff) | |
target/riscv: Set env->bins in gen_exception_illegal
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b151c20674..a10f3f939c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -240,6 +240,8 @@ static void generate_exception_mtval(DisasContext *ctx, int excp) static void gen_exception_illegal(DisasContext *ctx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } |