diff options
author | Víctor Colombo <victor.colombo@eldorado.org.br> | 2022-06-10 13:55:17 -0300 |
---|---|---|
committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
commit | 4e245a9e263e6272c5a47a46c770f3c3965cdf21 (patch) | |
tree | 37e67e52d60df8443e6d0d66be0f895258bbe4a9 /target/riscv | |
parent | d495e432c04a6394126c35cf96517749708b410f (diff) |
target/riscv: Remove condition guarding register zero for auipc and lui
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/insn_trans/trans_rvi.c.inc | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index f1342f30f8..c190a59f22 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) static bool trans_lui(DisasContext *ctx, arg_lui *a) { - if (a->rd != 0) { - gen_set_gpri(ctx, a->rd, a->imm); - } + gen_set_gpri(ctx, a->rd, a->imm); return true; } static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { - if (a->rd != 0) { - gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); - } + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); return true; } |