diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-03-19 14:22:46 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-19 14:22:46 +0000 |
| commit | 4dd6517e369828171290b65e11f6a45aeeed15af (patch) | |
| tree | 26ded616ea98684c7bac7ae2d1d26d1691e6b00f /target/openrisc | |
| parent | a1ba62a0f304291c96939cbf7c38e2ab68770326 (diff) | |
| parent | 3c6712eca07255803b61ca3d632f61a65c078c36 (diff) | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging
x86 and machine queue for 5.0 soft freeze
Bug fixes:
* memory encryption: Disable mem merge
(Dr. David Alan Gilbert)
Features:
* New EPYC CPU definitions (Babu Moger)
* Denventon-v2 CPU model (Tao Xu)
* New 'note' field on versioned CPU models (Tao Xu)
Cleanups:
* x86 CPU topology cleanups (Babu Moger)
* cpu: Use DeviceClass reset instead of a special CPUClass reset
(Peter Maydell)
# gpg: Signature made Wed 18 Mar 2020 01:16:43 GMT
# gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg: issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/x86-and-machine-pull-request:
hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
hw/i386: Update structures to save the number of nodes per package
hw/i386: Remove unnecessary initialization in x86_cpu_new
machine: Add SMP Sockets in CpuTopology
hw/i386: Consolidate topology functions
hw/i386: Introduce X86CPUTopoInfo to contain topology info
cpu: Use DeviceClass reset instead of a special CPUClass reset
machine/memory encryption: Disable mem merge
hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
i386: Add 2nd Generation AMD EPYC processors
i386: Add missing cpu feature bits in EPYC model
target/i386: Add new property note to versioned CPU models
target/i386: Add Denverton-v2 (no MPX) CPU model
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/openrisc')
| -rw-r--r-- | target/openrisc/cpu.c | 8 | ||||
| -rw-r--r-- | target/openrisc/cpu.h | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5cd04dafab..5528c0918f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,13 +41,13 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) info->print_insn = print_insn_or1k; } -/* CPUClass::reset() */ -static void openrisc_cpu_reset(CPUState *s) +static void openrisc_cpu_reset(DeviceState *dev) { + CPUState *s = CPU(dev); OpenRISCCPU *cpu = OPENRISC_CPU(s); OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); - occ->parent_reset(s); + occ->parent_reset(dev); memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); @@ -150,7 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); + device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index d9484b802f..f37a52e153 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -48,7 +48,7 @@ typedef struct OpenRISCCPUClass { /*< public >*/ DeviceRealize parent_realize; - void (*parent_reset)(CPUState *cpu); + DeviceReset parent_reset; } OpenRISCCPUClass; #define TARGET_INSN_START_EXTRA_WORDS 1 |