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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-02-07 13:35:58 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-03-06 22:23:09 +0100
commit1ea4a06af0f6578e5d0ddcea148503290b1c4907 (patch)
tree060b35cfbdf984ec058efb07d1815283b1058dd0 /target/openrisc
parent36861198754af7577c73cdb19e1e385c933bfdc8 (diff)
target: Use CPUArchState as interface to target-specific CPU state
While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
Diffstat (limited to 'target/openrisc')
-rw-r--r--target/openrisc/cpu.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 5711591520..a218e49f0e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -242,7 +242,7 @@ typedef struct CPUOpenRISCTLBContext {
} CPUOpenRISCTLBContext;
#endif
-typedef struct CPUOpenRISCState {
+typedef struct CPUArchState {
target_ulong shadow_gpr[16][32]; /* Shadow registers */
target_ulong pc; /* Program counter */
@@ -348,7 +348,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
-typedef CPUOpenRISCState CPUArchState;
typedef OpenRISCCPU ArchCPU;
#include "exec/cpu-all.h"