diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:06 +0100 |
| commit | cdfd14e86ab0b1ca29a702d13a8e4af2e902a9bf (patch) | |
| tree | 3314c60de44742421a68119e0328ac2e4b1cafef /target/arm/vfp.decode | |
| parent | b623d803dda805f07aadcbf098961fde27315c19 (diff) | |
target/arm: Convert the VCVT-to-f16 insns to decodetree
Convert the VCVTT and VCVTB instructions which convert from
f32 and f64 to f16 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
store of the right half of the input single-precision register
rather than doing a load/modify/store sequence on the full
32 bits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/vfp.decode')
| -rw-r--r-- | target/arm/vfp.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 53d9544f7c..b88d1d06f0 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -187,3 +187,9 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \ vd=%vd_sp vm=%vm_sp VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ vd=%vd_dp vm=%vm_sp + +# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit +VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ + vd=%vd_sp vm=%vm_sp +VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ + vd=%vd_sp vm=%vm_dp |