diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:45 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:04 +0100 |
| commit | 81f681106eabe21c55118a5a41999fb7387fb714 (patch) | |
| tree | 3668640c750484b058b7fb74f694443c2ea38212 /target/arm/vfp.decode | |
| parent | a9ab50011aeda2dd012da99069e078379315ea18 (diff) | |
target/arm: Convert VFP two-register transfer insns to decodetree
Convert the VFP two-register transfer instructions to decodetree
(in the v8 Arm ARM these are the "Advanced SIMD and floating-point
64-bit move" encoding group).
Again, we expand out the sequences involving gen_vfp_msr() and
gen_msr_vfp().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/vfp.decode')
| -rw-r--r-- | target/arm/vfp.decode | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index bb7de403df..134f1c9ef5 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -66,3 +66,8 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ vn=%vn_sp + +VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \ + vm=%vm_sp +VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ + vm=%vm_dp |