diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-28 19:33:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-01 11:19:32 +0100 |
| commit | 46a4b854525cb9f34a611f6ada6cdff1eab0ac2d (patch) | |
| tree | ed4928cfc83e2868883cc8570ca2e08ac3c4dbcc /target/arm/vfp.decode | |
| parent | f61e5c43b86907dea17f431b528d806659d62bcb (diff) | |
target/arm: Implement VFP fp16 VMOV between gp and halfprec registers
Implement the VFP fp16 variant of VMOV that transfers a 16-bit
value between a general purpose register and a VFP register.
Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later
only we have no need to replicate the old "updates CPSR.NZCV"
behaviour that the singleprec version of this insn does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-22-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/vfp.decode')
| -rw-r--r-- | target/arm/vfp.decode | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 9a79e99f1b..51f143b4a5 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -74,6 +74,7 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ vn=%vn_dp VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 +VMOV_half ---- 1110 000 l:1 .... rt:4 1001 . 001 0000 vn=%vn_sp VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp |