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authorRichard Henderson <richard.henderson@linaro.org>2022-06-20 10:51:52 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-06-27 11:18:17 +0100
commita3637e8882f9dbb00036ff77a88b841bd2580900 (patch)
treeed5b8dda8291d86f3df4abbe721731945344ab72 /target/arm/translate-a64.c
parentd5b1223ac1ddf8f706f5e6feaaa526df8287f8b1 (diff)
target/arm: Add PSTATE.{SM,ZA} to TB flags
These are required to determine if various insns are allowed to issue. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
-rw-r--r--target/arm/translate-a64.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8f609f46b6..5cf4a283ba 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14630,6 +14630,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->ata = EX_TBFLAG_A64(tb_flags, ATA);
dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE);
dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);
+ dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);
+ dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;