diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:52:03 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | 5d7953adcfb30196ba684d3af69271528630367f (patch) | |
| tree | aaca7c487f23e2990a7ef3441769ad7da25a170f /target/arm/translate-a64.c | |
| parent | 6ca54aa9a882ece5a6bcf5879f25bdcd7a95331f (diff) | |
target/arm: Add SVL to TB flags
We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c050ebe005..c86b97b1d4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14647,6 +14647,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; + dc->svl = (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); |