diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-06 13:02:34 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-09 11:47:54 +0100 |
| commit | 13954587ea240c305d43cffd1adc8959146f43fd (patch) | |
| tree | e8c4d40aa7dc11d69fd755303d1da5e8919b54d0 /target/arm/translate-a64.c | |
| parent | 3c29632feba7724be447b621f3527136e5c32744 (diff) | |
target/arm: Implement ESB instruction
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b80313670f..5a02e076b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1454,6 +1454,23 @@ static void handle_hint(DisasContext *s, uint32_t insn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], |