diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-05-20 16:28:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 16:43:25 +0100 |
| commit | b26b5629c0be4a9539833de4189184a224590d14 (patch) | |
| tree | 6ba883e488bf82896ec16e9cf518f7b3f2fe8369 /target/arm/machine.c | |
| parent | 7c3d47dab908ac1770726e68cf72e47bb5a9cbcb (diff) | |
target/arm: Make FPSCR.LTPSIZE writable for MVE
The M-profile FPSCR has an LTPSIZE field, but if MVE is not
implemented it is read-only and always reads as 4; this is how QEMU
currently handles it.
Make the field writable when MVE is implemented.
We can safely add the field to the MVE migration struct because
currently no CPUs enable MVE and so the migration struct is never
used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/machine.c')
| -rw-r--r-- | target/arm/machine.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/machine.c b/target/arm/machine.c index 62a71a3b64..81e30de824 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -332,6 +332,7 @@ static const VMStateDescription vmstate_m_mve = { .needed = mve_needed, .fields = (VMStateField[]) { VMSTATE_UINT32(env.v7m.vpr, ARMCPU), + VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), VMSTATE_END_OF_LIST() }, }; |