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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-19 11:56:39 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-05-19 11:56:39 -0700 |
| commit | 3a650ac995ca36fb9974b82ba50aac8d1fd18b6a (patch) | |
| tree | 28f7f8c3a8d29404c5be34e32e93db3c00f7f265 /docs | |
| parent | 78ac2eebbab9150edf5d0d00e3648f5ebb599001 (diff) | |
| parent | fab8ad39fb75a0d9f097db67b2a334444754e88e (diff) | |
Merge tag 'pull-target-arm-20220519' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Implement FEAT_S2FWB
* Implement FEAT_IDST
* Drop unsupported_encoding() macro
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
* Fix aarch64 debug register names
* hw/adc/zynq-xadc: Use qemu_irq typedef
* target/arm/helper.c: Delete stray obsolete comment
* Make number of counters in PMCR follow the CPU
* hw/arm/virt: Fix dtb nits
* ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
* target/arm: Fix PAuth keys access checks for disabled SEL2
* Enable FEAT_HCX for -cpu max
* Use FIELD definitions for CPACR, CPTR_ELx
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# gpg: Signature made Thu 19 May 2022 10:35:53 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20220519' of https://git.linaro.org/people/pmaydell/qemu-arm: (22 commits)
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
target/arm: Enable FEAT_HCX for -cpu max
target/arm: Fix PAuth keys access checks for disabled SEL2
ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
hw/arm/virt: Fix incorrect non-secure flash dtb node name
target/arm: Make number of counters in PMCR follow the CPU
target/arm/helper.c: Delete stray obsolete comment
hw/adc/zynq-xadc: Use qemu_irq typedef
Fix aarch64 debug register names.
hw/intc/arm_gicv3: Provide ich_num_aprs()
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
hw/intc/arm_gicv3: Support configurable number of physical priority bits
hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
target/arm: Drop unsupported_encoding() macro
target/arm: Implement FEAT_IDST
target/arm: Enable FEAT_S2FWB for -cpu max
target/arm: Implement FEAT_S2FWB
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/system/arm/emulation.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8ed466bf68..3e95bba0d2 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -31,6 +31,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IDST (ID space trap handling) - FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) @@ -52,6 +53,7 @@ the following architecture extensions: - FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) +- FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) |