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| author | Yang Weijiang <weijiang.yang@intel.com> | 2022-02-15 14:52:58 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-05-14 12:32:41 +0200 |
| commit | c3c67679f65903b7d1fe25da8fc4e163878ab2b9 (patch) | |
| tree | 18b04e655a77ca60f39ec21ac1bcfa06e8653895 /crypto | |
| parent | d19d6ffa07100f5015dc1c708d6c811354a13d7f (diff) | |
target/i386: Support Arch LBR in CPUID enumeration
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-9-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions