blob: 6d17cd53a0c14373e79b358a7f5f167ff52ca8ba (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
//=- X86RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
/// General Purpose Registers: RAX, RCX,...
def GPRRegBank : RegisterBank<"GPR", [GR64]>;
/// Floating Point/Vector Registers
def VECRRegBank : RegisterBank<"VECR", [VR512]>;
|
