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path: root/llvm/lib/Target/X86/X86ScheduleBtVer2.td
AgeCommit message (Expand)Author
2018-10-12[tblgen][llvm-mca] Add the ability to describe move elimination candidates vi...Andrea Di Biagio
2018-10-05[X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957)Simon Pilgrim
2018-10-03[X86][Btver2] Fix MMX PSHUFB scheduleSimon Pilgrim
2018-10-03[X86][Btver2] Most RMW instructions don't require an additional uopSimon Pilgrim
2018-10-02[X86][Btver2] Fix BLENDV and AESDEC schedulesSimon Pilgrim
2018-10-01[X86][Btver2] Fix BT(C|R|S)mr & BT(C|R|S)mi schedule latency + uop countsSimon Pilgrim
2018-10-01[X86] Create schedule classes for BT(C|R|S)mi and BT(C|R|S)mr instructionsSimon Pilgrim
2018-10-01[X86][Btver2] Fix BTmr schedule uop countsSimon Pilgrim
2018-10-01[X86] Create schedule classes for BTmi and BTmr instructionsSimon Pilgrim
2018-10-01[X86][Btver2] Fix masked load scheduleSimon Pilgrim
2018-10-01[X86][BtVer2] Teach how to identify zero-idiom VPERM2F128rr instructions.Andrea Di Biagio
2018-09-30[X86][Btver2] Fix PCmpIStrI/PCmpIStrM schedulesSimon Pilgrim
2018-09-30[X86][BtVer2] Add the ability to add additional uops for folded instructionsSimon Pilgrim
2018-09-28[X86][Btver2] PSUBS/PSUBUS instructions are zero-idiomsSimon Pilgrim
2018-09-28[X86][Btver2] CVTSS2I/CVTSD2I - add missing JFPU0 pipeSimon Pilgrim
2018-09-28[X86][Btver2] Fix BSF/BSR scheduleSimon Pilgrim
2018-09-28[X86][BtVer2] Fix PHMINPOS schedule resources typoSimon Pilgrim
2018-09-27[X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim
2018-09-27[X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1Simon Pilgrim
2018-09-27[X86] Split BT and BTC/BTR/BTS scheduler classesSimon Pilgrim
2018-09-27[X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT)Simon Pilgrim
2018-09-27[X86][Btver2] TZCNT instructions take 2uops not 1Simon Pilgrim
2018-09-24[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)Simon Pilgrim
2018-09-23[X86] Split WriteShift/WriteRotate schedule classes by CL usage.Simon Pilgrim
2018-09-23[X86] Add WriteRotate schedule class, splitting off from WriteShift.Simon Pilgrim
2018-09-21[X86][BtVer2] Fix latency and resource cycles of AVX 256-bit zero-idioms.Andrea Di Biagio
2018-09-19[TableGen][SubtargetEmitter] Add the ability for processor models to describe...Andrea Di Biagio
2018-09-14[X86][BMI1] Fix BLSI/BLSMSK/BLSR BMI1 scheduling on btver2Simon Pilgrim
2018-09-14[X86][BMI1] Add scheduler class for BLSI/BLSMSK/BLSR BMI1 instructionsSimon Pilgrim
2018-08-31[X86][BtVer2] Remove wrong ReadAdvance from AVX vbroadcast(ss|sd|f128) instru...Andrea Di Biagio
2018-08-31[X86][BtVer2] Fix WriteFShuffle256 schedule write info.Andrea Di Biagio
2018-08-30[X86] Improved sched model for X86 CMPXCHG* instructions.Andrew V. Tischenko
2018-08-13[X86][BtVer2] Use NoSchedPredicate to model default transitions in variant sc...Andrea Di Biagio
2018-08-09[X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.Andrew V. Tischenko
2018-08-01[X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko
2018-07-31[X86] WriteBSWAP sched classes are reg-reg only.Simon Pilgrim
2018-07-31Revert r338365: [X86] Improved sched models for X86 BT*rr instructions.Simon Pilgrim
2018-07-31[X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko
2018-07-31[X86] Improved sched models for X86 SHLD/SHRD* instructions.Andrew V. Tischenko
2018-07-20Improved sched model for X86 BSWAP* instrs.Andrew V. Tischenko
2018-07-19[X86][BtVer2] correctly model the latency/throughput of LEA instructions.Andrea Di Biagio
2018-07-15[llvm-mca][BtVer2] teach how to identify false dependencies on partially writtenAndrea Di Biagio
2018-07-08[X86][Nearly NFC] Split SHLD/SHRD into their own WriteShiftDouble classRoman Lebedev
2018-07-08[X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR.Roman Lebedev
2018-06-20[X86] Add sched class WriteLAHFSAHF and fix values.Clement Courbet
2018-06-18[X86][BtVer2] Flag AVX2+ scheduler classes as unsupportedSimon Pilgrim
2018-06-11[X86] Fix skylake server scheduling info.Clement Courbet
2018-06-11[X86] Explicitly mark unsupported classes in scheduling models.Clement Courbet
2018-06-08[X86][BtVer2] Add support for all SUB/XOR 32/64 scalar instructions that shou...Simon Pilgrim
2018-06-07[X86][NFC] Fix harmless typo in BtVer2 model.Clement Courbet
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