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path: root/llvm/lib/Target/X86/X86SchedSandyBridge.td
AgeCommit message (Expand)Author
2018-11-09[X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.Clement Courbet
2018-10-05[X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957)Simon Pilgrim
2018-10-02[X86] Remove unnecessary BT(C/R/S)m(i/r) scheduler overridesSimon Pilgrim
2018-10-01[X86] Create schedule classes for BT(C|R|S)mi and BT(C|R|S)mr instructionsSimon Pilgrim
2018-10-01[X86] Remove unnecessary BTmi/BTmr scheduler overridesSimon Pilgrim
2018-10-01[X86] Create schedule classes for BTmi and BTmr instructionsSimon Pilgrim
2018-10-01[X86][Sched] Update scheduling information for VZEROALL on HWS, BDW, SKX, SNB.Clement Courbet
2018-09-27[X86] Split BT and BTC/BTR/BTS scheduler classesSimon Pilgrim
2018-09-25Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim
2018-09-24[X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim
2018-09-24[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)Simon Pilgrim
2018-09-23[X86] Split WriteShift/WriteRotate schedule classes by CL usage.Simon Pilgrim
2018-09-23[X86] Remove unnecessary WriteRotate override. NFCI.Simon Pilgrim
2018-09-23Fix line ending mismatches. NFCI.Simon Pilgrim
2018-09-23[X86] Added missing RCL/RCR schedule overrides to the generic SNB modelSimon Pilgrim
2018-09-23[X86] Add WriteRotate schedule class, splitting off from WriteShift.Simon Pilgrim
2018-09-21[X86][Sched] Add zero idiom sched data to the SNB model.Clement Courbet
2018-09-14[X86][BMI1] Add scheduler class for BLSI/BLSMSK/BLSR BMI1 instructionsSimon Pilgrim
2018-08-30[X86] Improved sched model for X86 CMPXCHG* instructions.Andrew V. Tischenko
2018-08-18[X86] Replace all single match schedule class instregexs with instrs entriesSimon Pilgrim
2018-08-18[X86] Merge shift/rotate schedule class instregexsSimon Pilgrim
2018-08-09[X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.Andrew V. Tischenko
2018-08-01[X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko
2018-07-31[X86] WriteBSWAP sched classes are reg-reg only.Simon Pilgrim
2018-07-31Revert r338365: [X86] Improved sched models for X86 BT*rr instructions.Simon Pilgrim
2018-07-31[X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko
2018-07-31[X86] Improved sched models for X86 SHLD/SHRD* instructions.Andrew V. Tischenko
2018-07-20Improved sched model for X86 BSWAP* instrs.Andrew V. Tischenko
2018-07-08[X86][Nearly NFC] Split SHLD/SHRD into their own WriteShiftDouble classRoman Lebedev
2018-07-08[X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR.Roman Lebedev
2018-06-20[X86] Add sched class WriteLAHFSAHF and fix values.Clement Courbet
2018-06-11[X86] Fix skylake server scheduling info.Clement Courbet
2018-06-11[X86] Explicitly mark unsupported classes in scheduling models.Clement Courbet
2018-05-31[X86] Introduce WriteFLDC for x87 constant loads.Clement Courbet
2018-05-31[X86] Extract latency of fldz/fld1 in separate classes.Clement Courbet
2018-05-29[X86][Sched] Add InstRW for CLC on Intel after SNB.Clement Courbet
2018-05-25[X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286)Simon Pilgrim
2018-05-18[X86] Add GPR<->XMM Schedule TagsSimon Pilgrim
2018-05-17[X86] Split WriteCMOV + WriteCMOV2 scheduler classesSimon Pilgrim
2018-05-17[X86] Split WriteADC/WriteADCRMW scheduler classesSimon Pilgrim
2018-05-17[X86][SNB] Minor scheduler cleanupSimon Pilgrim
2018-05-16[X86][SNB] Remove unnecessary CVT InstRW overridesSimon Pilgrim
2018-05-16[X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classesSimon Pilgrim
2018-05-15[X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classesSimon Pilgrim
2018-05-15[X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classesSimon Pilgrim
2018-05-14[X86] Add NT load/store scheduler classesSimon Pilgrim
2018-05-12[X86] Add WriteFCMOV scheduler class for x87 CMOVsSimon Pilgrim
2018-05-11[X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector widthSimon Pilgrim
2018-05-10[X86] Convert/Merge more instregex patterns to reduce InstrRW compile time.Simon Pilgrim
2018-05-10[X86][SNB] Fix typo in PEXTRDmr instregex, was missing VPEXTRDmr.Simon Pilgrim
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