ci/llvm-monorepo.git - [no description]

Age	Commit message (Expand)	Author
2018-10-02	[X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign ...	Craig Topper
2018-06-16	[X86] More additions to the load folding tables based on the autogenerated ta...	Craig Topper
2018-04-13	[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.	Craig Topper
2018-04-12	[X86] Remove gpr shift/extension schedule itineraries (PR37093)	Simon Pilgrim
2018-03-20	[X86] Rename MOVSX32_NOREXrr8 to MOVSX32rr8_NOREX so that the scheduler model...	Craig Topper
2018-01-23	[X86] Remove 'NOREX' comment from the printing of _NOREX instructions.	Craig Topper
2017-12-11	Normalize line endings. NFCI.	Simon Pilgrim
2017-11-15	[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class	Simon Pilgrim
2017-09-27	Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instru...	Craig Topper
2017-09-26	Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into post...	Craig Topper
2017-09-26	Revert "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos...	Benjamin Kramer
2017-09-25	[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like th...	Craig Topper
2016-01-07	[X86] Add OpSize32 to MOVSX32_NOREX instructions to match their other versions.	Craig Topper
2016-01-07	[X86] Add hasSideEffects=0 and mayLoad=1 to MOVZX64* instructions. While ther...	Craig Topper
2015-02-03	[X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it...	Craig Topper
2014-11-26	Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.	Craig Topper
2014-11-03	[X86] 8bit divrem: Improve codegen for AH register extraction.	Ahmed Bougacha
2014-02-02	Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ...	Craig Topper
2014-01-08	[x86] Add OpSize16 to instructions that need it	David Woodhouse
2013-09-13	Adds support for Atom Silvermont (SLM) - -march=slm	Preston Gurd
2013-05-30	X86: change zext moves to use sub-register infrastructure.	Tim Northover
2013-03-26	Annotate the remaining x86 instructions with SchedRW lists.	Jakob Stoklund Olesen
2013-03-19	Annotate X86InstrExtension.td with SchedRW lists.	Jakob Stoklund Olesen
2012-07-30	Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad	Craig Topper
2012-07-30	Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnl...	Craig Topper
2012-02-29	Intel Atom instruction itineraries for mov sign extension and mov zero extens...	Andrew Trick
2012-02-18	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...	Jia Liu
2011-10-07	Constrain both operands on MOVZX32_NOREXrr8.	Jakob Stoklund Olesen
2011-05-20	Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.	Stuart Hastings
2011-05-19	Reverting 131641 to investigate 'bot complaint.	Stuart Hastings
2011-05-19	Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be	Stuart Hastings
2010-11-01	make the asm matcher emitter reject instructions that have comments	Chris Lattner
2010-10-31	two changes: make the asmmatcher generator ignore ARM pseudos properly,	Chris Lattner
2010-10-05	add new file	Chris Lattner