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-rw-r--r--llvm/lib/Target/X86/X86RegisterInfo.td6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 0c1b05fd3ab..aa20273f89a 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -522,10 +522,16 @@ def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
// faster on common hardware. In reality, this should be controlled by a
// command line option or something.
+
def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>;
def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
+// st(7) may be is not allocatable.
+def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> {
+ let isAllocatable = 0;
+}
+
// Floating point stack registers (these are not allocatable by the
// register allocator - the floating point stackifier is responsible
// for transforming FPn allocations to STn registers)