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authorCraig Topper <craig.topper@intel.com>2018-06-18 05:00:50 +0000
committerCraig Topper <craig.topper@intel.com>2018-06-18 05:00:50 +0000
commiteb0067f16024c63f187e7152ad76ab63ca602fca (patch)
tree8b728b1ec5543c31526dfab61acd737fee3e0f22 /llvm/lib/Target/X86/X86InstrMMX.td
parent66d5a148adc5ea3fcaeabae8f4bf795cebfab61f (diff)
[X86] Add '.s' aliases to the assembler for the various redundant move encodings to match gas and our EVEX instructions.
We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions. Also remove the vpextrw.s EVEX alias. That's not something gas implements.
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrMMX.td')
-rw-r--r--llvm/lib/Target/X86/X86InstrMMX.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td
index c0d6b070c86..87ce64615c4 100644
--- a/llvm/lib/Target/X86/X86InstrMMX.td
+++ b/llvm/lib/Target/X86/X86InstrMMX.td
@@ -206,9 +206,6 @@ def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
(ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
[]>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
-// These are 64 bit moves, but since the OS X assembler doesn't
-// recognize a register-register movq, we write them as
-// movd.
let isBitcast = 1 in {
def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
(outs GR64:$dst), (ins VR64:$src),
@@ -225,6 +222,9 @@ def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
} // SchedRW, hasSideEffects, isMoveReg
} // isBitcast
+def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
+ (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
(outs), (ins i64mem:$dst, VR64:$src),