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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-11 16:38:59 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-11 16:38:59 +0000 |
commit | 7d50b6e9d69187044435a74ce77dccb33af7bf4e (patch) | |
tree | 7b44ed6c95a4e1d9f19c9c51eaf619d73f70c5e7 /llvm/lib/Target/X86/X86InstrMMX.td | |
parent | 18b90c75f17f691cdf529a7a5b66ce4980d288e1 (diff) |
[X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classes
Fixes an issue on SLM/Btver2 where we had instructions were being treated as scalar loads/stores
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrMMX.td')
-rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 0b4ad80d08c..57a5bee2b26 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -204,7 +204,7 @@ def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", - []>, Sched<[WriteLoad]>; + []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>; // These are 64 bit moves, but since the OS X assembler doesn't // recognize a register-register movq, we write them as @@ -228,16 +228,16 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movq\t{$src, $dst|$dst, $src}", []>, - Sched<[WriteStore]>; + Sched<[SchedWriteVecMoveLS.MMX.MR]>; -let SchedRW = [WriteLoad] in { +let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in { let canFoldAsLoad = 1 in def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", [(set VR64:$dst, (load_mmx addr:$src))]>; } // SchedRW -let SchedRW = [WriteStore] in +let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movq\t{$src, $dst|$dst, $src}", [(store (x86mmx VR64:$src), addr:$dst)]>; @@ -272,7 +272,7 @@ let Predicates = [HasSSE1] in def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movntq\t{$src, $dst|$dst, $src}", [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>, - Sched<[WriteStore]>; + Sched<[SchedWriteVecMoveLS.MMX.MR]>; let Predicates = [HasMMX] in { let AddedComplexity = 15 in |