diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-01-24 17:58:51 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-24 17:58:51 +0000 |
| commit | 782ff3a08d6ea34c042986e296cc7500183200d8 (patch) | |
| tree | b760ef3d74c30a288101e094d22612a05757699d /llvm/lib/Target/X86/X86InstrMMX.td | |
| parent | 374230cf6f696681470ee86ca2c0281e589f604b (diff) | |
[X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrMMX.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 1a1f64e3a0b..7a4a9eec123 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -599,30 +599,30 @@ let Constraints = "$src1 = $dst" in { // Extract / Insert let Predicates = [HasSSE1] in -def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg, - (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), - "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", - [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, - imm:$src2))], - IIC_MMX_PEXTR>, Sched<[WriteShuffle]>; +def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, + (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, + imm:$src2))], + IIC_MMX_PEXTR>, Sched<[WriteShuffle]>; let Constraints = "$src1 = $dst" in { let Predicates = [HasSSE1] in { - def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg, - (outs VR64:$dst), - (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), - "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, - GR32orGR64:$src2, imm:$src3))], - IIC_MMX_PINSRW>, Sched<[WriteShuffle]>; - - def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem, - (outs VR64:$dst), - (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3), - "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, - (i32 (anyext (loadi16 addr:$src2))), - imm:$src3))], - IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>; + def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg, + (outs VR64:$dst), + (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + GR32orGR64:$src2, imm:$src3))], + IIC_MMX_PINSRW>, Sched<[WriteShuffle]>; + + def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem, + (outs VR64:$dst), + (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + (i32 (anyext (loadi16 addr:$src2))), + imm:$src3))], + IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>; } } |