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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-02-12 15:52:59 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-02-12 15:52:59 +0000 |
| commit | 6d43f861d772fe462f59d0c39123a80f89e0a380 (patch) | |
| tree | e9431f7d2dc1d5fb61ec880df836e3a6e8b5cc10 /llvm/lib/Target/X86/X86InstrMMX.td | |
| parent | afd7a7adc632b855eea68b0eaeb035d3466ec3f0 (diff) | |
[X86][MMX] Add missing scheduling class tag for EMMS/FEMMS
We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639).
AMD targets can perform these a lot quicker than WriteMicrocoded so will need an override in the models.
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrMMX.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index f6bff658e56..46dfdb9e319 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -221,6 +221,8 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, // MMX EMMS Instruction //===----------------------------------------------------------------------===// +// FIXME: Is there a better scheduler class for EMMS/FEMMS? +let SchedRW = [WriteMicrocoded] in def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)], IIC_MMX_EMMS>; |