diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-03 17:56:43 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-03 17:56:43 +0000 |
| commit | 2b144c5c9299aa10666f479ae4270b3ee01f453b (patch) | |
| tree | 7d109d4ff8c9fc9c07999b79aa116061b43f6261 /llvm/lib/Target/X86/X86InstrMMX.td | |
| parent | 9bbb7c6615e06ed67b0d9bec7251e7694c6fa027 (diff) | |
[X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes
This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness.
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrMMX.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index c21c00afbfb..c410ddb4c60 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -52,7 +52,8 @@ let Constraints = "$src1 = $dst" in { multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, string OpcodeStr, Intrinsic IntId, - Intrinsic IntId2, X86FoldableSchedWrite sched> { + Intrinsic IntId2, X86FoldableSchedWrite sched, + X86FoldableSchedWrite schedImm> { def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), @@ -68,7 +69,7 @@ let Constraints = "$src1 = $dst" in { (ins VR64:$src1, i32u8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))]>, - Sched<[sched]>; + Sched<[schedImm]>; } } @@ -412,30 +413,38 @@ defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, // Shift Instructions defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_mmx_psll_w, int_x86_mmx_pslli_w, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_mmx_psll_d, int_x86_mmx_pslli_d, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_mmx_psll_q, int_x86_mmx_pslli_q, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_mmx_psra_w, int_x86_mmx_psrai_w, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_mmx_psra_d, int_x86_mmx_psrai_d, - SchedWriteVecShift.MMX>; + SchedWriteVecShift.MMX, + SchedWriteVecShiftImm.MMX>; // Comparison Instructions defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, |