summaryrefslogtreecommitdiff
path: root/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
diff options
context:
space:
mode:
authorTom Stellard <tstellar@redhat.com>2018-11-13 04:49:21 +0000
committerTom Stellard <tstellar@redhat.com>2018-11-13 04:49:21 +0000
commit27b9ba425ee69146079e14333db0dcbb1503da7b (patch)
treef684020dfe20d3589e2a5ab524fa62aa09b1e8f2 /llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
parentb93f16ecbe94976bd526ac5fbc51733585253038 (diff)
Merging r340927:
------------------------------------------------------------------------ r340927 | vstefanovic | 2018-08-29 07:07:14 -0700 (Wed, 29 Aug 2018) | 14 lines [mips] Prevent shrink-wrap for BuildPairF64, ExtractElementF64 when they use $sp For a certain combination of options, BuildPairF64_{64}, ExtractElementF64{_64} may be expanded into instructions using stack. Add implicit operand $sp for such cases so that ShrinkWrapping doesn't move prologue setup below them. Fixes MultiSource/Benchmarks/MallocBench/cfrac for '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfpxx -mnan=2008' and '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfp64 -mnan=2008 -mno-odd-spreg'. Differential Revision: https://reviews.llvm.org/D50986 ------------------------------------------------------------------------
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 599c1e913ac..cf2899dd375 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -238,6 +238,18 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
case Mips::WRDSP:
addDSPCtrlRegOperands(true, MI, MF);
break;
+ case Mips::BuildPairF64_64:
+ case Mips::ExtractElementF64_64:
+ if (!Subtarget->useOddSPReg()) {
+ MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
+ break;
+ }
+ // fallthrough
+ case Mips::BuildPairF64:
+ case Mips::ExtractElementF64:
+ if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
+ MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
+ break;
default:
replaceUsesWithZeroReg(MRI, MI);
}