diff options
author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-11-28 12:00:20 +0000 |
---|---|---|
committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-11-28 12:00:20 +0000 |
commit | fef3d10f39ab2bf16ddbe1f1df14cfd2c199f370 (patch) | |
tree | b396c7e9a8bffc457123b4192631e67769e5a7bb /llvm/lib/Target/Lanai | |
parent | c2db91336ab0b59e7ee0b0eb308105ec4dc86075 (diff) |
[CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand
Currently, instructions doing memory accesses through a base operand that is
not a register can not be analyzed using `TII::getMemOpBaseRegImmOfs`.
This means that functions such as `TII::shouldClusterMemOps` will bail
out on instructions using an FI as a base instead of a register.
The goal of this patch is to refactor all this to return a base
operand instead of a base register.
Then in a separate patch, I will add FI support to the mem op clustering
in the MachineScheduler.
Differential Revision: https://reviews.llvm.org/D54846
Diffstat (limited to 'llvm/lib/Target/Lanai')
-rw-r--r-- | llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 27 | ||||
-rw-r--r-- | llvm/lib/Target/Lanai/LanaiInstrInfo.h | 12 |
2 files changed, 21 insertions, 18 deletions
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index a18352738e1..196768fdc56 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -101,12 +101,12 @@ bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint( // the width doesn't overlap the offset of a higher memory access, // then the memory accesses are different. const TargetRegisterInfo *TRI = &getRegisterInfo(); - unsigned BaseRegA = 0, BaseRegB = 0; + MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; int64_t OffsetA = 0, OffsetB = 0; unsigned int WidthA = 0, WidthB = 0; - if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && - getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { - if (BaseRegA == BaseRegB) { + if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && + getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { + if (BaseOpA->isIdenticalTo(*BaseOpB)) { int LowOffset = std::min(OffsetA, OffsetB); int HighOffset = std::max(OffsetA, OffsetB); int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; @@ -755,9 +755,9 @@ unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI, return 0; } -bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth( - MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, - const TargetRegisterInfo * /*TRI*/) const { +bool LanaiInstrInfo::getMemOperandWithOffsetWidth( + MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, + unsigned &Width, const TargetRegisterInfo * /*TRI*/) const { // Handle only loads/stores with base register followed by immediate offset // and with add as ALU op. if (LdSt.getNumOperands() != 4) @@ -787,14 +787,17 @@ bool LanaiInstrInfo::getMemOpBaseRegImmOfsWidth( break; } - BaseReg = LdSt.getOperand(1).getReg(); + BaseOp = &LdSt.getOperand(1); Offset = LdSt.getOperand(2).getImm(); + assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base " + "operands of type register."); return true; } -bool LanaiInstrInfo::getMemOpBaseRegImmOfs( - MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, - const TargetRegisterInfo *TRI) const { +bool LanaiInstrInfo::getMemOperandWithOffset(MachineInstr &LdSt, + MachineOperand *&BaseOp, + int64_t &Offset, + const TargetRegisterInfo *TRI) const { switch (LdSt.getOpcode()) { default: return false; @@ -808,6 +811,6 @@ bool LanaiInstrInfo::getMemOpBaseRegImmOfs( case Lanai::LDBs_RI: case Lanai::LDBz_RI: unsigned Width; - return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); + return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); } } diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index fe22fde2470..bdcf9a361b5 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -68,13 +68,13 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; - bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, - int64_t &Offset, - const TargetRegisterInfo *TRI) const override; + bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp, + int64_t &Offset, + const TargetRegisterInfo *TRI) const override; - bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, - int64_t &Offset, unsigned &Width, - const TargetRegisterInfo *TRI) const; + bool getMemOperandWithOffsetWidth(MachineInstr &LdSt, MachineOperand *&BaseOp, + int64_t &Offset, unsigned &Width, + const TargetRegisterInfo *TRI) const; std::pair<unsigned, unsigned> decomposeMachineOperandsTargetFlags(unsigned TF) const override; |