[LLD][ELF] - Support MSP430.

Patch by Michael Skvortsov!

This change adds a basic support for linking static MSP430 ELF code.
Implemented relocation types are intended to correspond to the BFD.

Differential revision: https://reviews.llvm.org/D56535

7 files changed, 105 insertions, 0 deletions

diff --git a/lld/ELF/Arch/MSP430.cpp b/lld/ELF/Arch/MSP430.cpp
new file mode 100644
index 00000000000..073283374f8
--- /dev/null
+++ b/lld/ELF/Arch/MSP430.cpp
@@ -0,0 +1,94 @@
+//===- MSP430.cpp ---------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// The MSP430 is a 16-bit microcontroller RISC architecture. The instruction set
+// has only 27 core instructions orthogonally augmented with a variety
+// of addressing modes for source and destination operands. Entire address space
+// of MSP430 is 64KB (the extended MSP430X architecture is not considered here).
+// A typical MSP430 MCU has several kilobytes of RAM and ROM, plenty
+// of peripherals and is generally optimized for a low power consumption.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "lld/Common/ErrorHandler.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class MSP430 final : public TargetInfo {
+public:
+  MSP430();
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+} // namespace
+
+MSP430::MSP430() {
+  // mov.b #0, r3
+  TrapInstr = {0x43, 0x43};
+}
+
+RelExpr MSP430::getRelExpr(RelType Type, const Symbol &S,
+                           const uint8_t *Loc) const {
+  switch (Type) {
+  case R_MSP430_10_PCREL:
+  case R_MSP430_16_PCREL:
+  case R_MSP430_16_PCREL_BYTE:
+  case R_MSP430_2X_PCREL:
+  case R_MSP430_RL_PCREL:
+  case R_MSP430_SYM_DIFF:
+    return R_PC;
+  default:
+    return R_ABS;
+  }
+}
+
+void MSP430::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+  switch (Type) {
+  case R_MSP430_8:
+    checkIntUInt(Loc, Val, 8, Type);
+    *Loc = Val;
+    break;
+  case R_MSP430_16:
+  case R_MSP430_16_PCREL:
+  case R_MSP430_16_BYTE:
+  case R_MSP430_16_PCREL_BYTE:
+    checkIntUInt(Loc, Val, 16, Type);
+    write16le(Loc, Val);
+    break;
+  case R_MSP430_32:
+    checkIntUInt(Loc, Val, 32, Type);
+    write32le(Loc, Val);
+    break;
+  case R_MSP430_10_PCREL: {
+    int16_t Offset = ((int16_t)Val >> 1) - 1;
+    checkInt(Loc, Offset, 10, Type);
+    write16le(Loc, (read16le(Loc) & 0xFC00) | (Offset & 0x3FF));
+    break;
+  }
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
+  }
+}
+
+TargetInfo *elf::getMSP430TargetInfo() {
+  static MSP430 Target;
+  return &Target;
+}
diff --git a/lld/ELF/CMakeLists.txt b/lld/ELF/CMakeLists.txt
index 51fc1e5646a..a1c23b0d49a 100644
--- a/lld/ELF/CMakeLists.txt
+++ b/lld/ELF/CMakeLists.txt
@@ -15,6 +15,7 @@ add_lld_library(lldELF
   Arch/Hexagon.cpp
   Arch/Mips.cpp
   Arch/MipsArchTree.cpp
+  Arch/MSP430.cpp
   Arch/PPC.cpp
   Arch/PPC64.cpp
   Arch/RISCV.cpp
diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp
index a85e5e6afb0..e4d1dec7cbc 100644
--- a/lld/ELF/InputFiles.cpp
+++ b/lld/ELF/InputFiles.cpp
@@ -1081,6 +1081,8 @@ static uint8_t getBitcodeMachineKind(StringRef Path, const Triple &T) {
   case Triple::mips64:
   case Triple::mips64el:
     return EM_MIPS;
+  case Triple::msp430:
+    return EM_MSP430;
   case Triple::ppc:
     return EM_PPC;
   case Triple::ppc64:
diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp
index a6293548a41..01073a62cfd 100644
--- a/lld/ELF/Target.cpp
+++ b/lld/ELF/Target.cpp
@@ -75,6 +75,8 @@ TargetInfo *elf::getTarget() {
     default:
       llvm_unreachable("unsupported MIPS target");
     }
+  case EM_MSP430:
+    return getMSP430TargetInfo();
   case EM_PPC:
     return getPPCTargetInfo();
   case EM_PPC64:
diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h
index e7a31e76327..685ad05ecd6 100644
--- a/lld/ELF/Target.h
+++ b/lld/ELF/Target.h
@@ -146,6 +146,7 @@ TargetInfo *getAMDGPUTargetInfo();
 TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
 TargetInfo *getHexagonTargetInfo();
+TargetInfo *getMSP430TargetInfo();
 TargetInfo *getPPC64TargetInfo();
 TargetInfo *getPPCTargetInfo();
 TargetInfo *getRISCVTargetInfo();
diff --git a/lld/test/ELF/Inputs/msp430.s b/lld/test/ELF/Inputs/msp430.s
new file mode 100644
index 00000000000..79e707a5c28
--- /dev/null
+++ b/lld/test/ELF/Inputs/msp430.s
@@ -0,0 +1,4 @@
+  .text
+  .global _start
+_start:
+  nop
diff --git a/lld/test/lit.cfg.py b/lld/test/lit.cfg.py
index 967cba1e01c..e53ff874003 100644
--- a/lld/test/lit.cfg.py
+++ b/lld/test/lit.cfg.py
@@ -72,6 +72,7 @@ llvm_config.feature_config(
                           'AVR': 'avr',
                           'Hexagon': 'hexagon',
                           'Mips': 'mips',
+                          'MSP430': 'msp430',
                           'PowerPC': 'ppc',
                           'RISCV': 'riscv',
                           'Sparc': 'sparc',