diff options
| author | Nirav Dave <niravd@google.com> | 2019-01-15 17:09:14 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2019-01-15 17:09:14 +0000 |
| commit | f6aec44071b7efd716ed31154c63f53d94becfed (patch) | |
| tree | 0070a7a513931b643f77bc030537f144f012bc08 | |
| parent | c8da389137b1260c8dceac52c413adf3b12eb50e (diff) | |
[X86] Fix register class for assembly constraints to ST(7). NFCI.
Modify getRegForInlineAsmConstraint to return special singleton
register class when a constraint references ST(7) not RFP80 for which
ST(7) is not a member.
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 6 |
2 files changed, 13 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5404c4c0846..de11f090b31 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -42477,14 +42477,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, if (!Res.second) { // Map st(0) -> st(7) -> ST0 if (Constraint.size() == 7 && Constraint[0] == '{' && - tolower(Constraint[1]) == 's' && - tolower(Constraint[2]) == 't' && + tolower(Constraint[1]) == 's' && tolower(Constraint[2]) == 't' && Constraint[3] == '(' && (Constraint[4] >= '0' && Constraint[4] <= '7') && - Constraint[5] == ')' && - Constraint[6] == '}') + Constraint[5] == ')' && Constraint[6] == '}') { + // st(7) is not allocatable and thus not a member of RFP80. Return + // singleton class in cases where we have a reference to it. + if (Constraint[4] == '7') + return std::make_pair(X86::FP7, &X86::RFP80_7RegClass); return std::make_pair(X86::FP0 + Constraint[4] - '0', &X86::RFP80RegClass); + } // GCC allows "st(0)" to be called just plain "st". if (StringRef("{st}").equals_lower(Constraint)) diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index 0c1b05fd3ab..aa20273f89a 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -522,10 +522,16 @@ def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; // faster on common hardware. In reality, this should be controlled by a // command line option or something. + def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; +// st(7) may be is not allocatable. +def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> { + let isAllocatable = 0; +} + // Floating point stack registers (these are not allocatable by the // register allocator - the floating point stackifier is responsible // for transforming FPn allocations to STn registers) |