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authorLinus Torvalds <torvalds@linux-foundation.org>2022-08-02 11:04:41 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2022-08-02 11:04:41 -0700
commit530c28df03e701618949bedf445b1c3c90854ea9 (patch)
treefae58617b02952525f258b17fcb63a3c84acee8c /Documentation
parent0805c6fb39f66e01cb0adccfae8d9e0615c70fd7 (diff)
parent8933d30c5f468d6cc1e4bf9bb535149da35f202e (diff)
Merge tag 'pwm/for-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding: "After v5.19 had all drivers converted to the new atomic API and nobody has reported any breakage, this set of changes starts by dropping the legacy support. Some existing drivers get improvements and broader chip support and a new driver is added that emulates a PWM controller using a clock output. Other than that there's the usual bits of cleanups and minor fixes" * tag 'pwm/for-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (21 commits) pwm: lpc18xx: Fix period handling pwm: lpc18xx: Convert to use dev_err_probe() pwm: twl-led: Document some limitations and link to the reference manual MAINTAINERS: Remove myself as PWM maintainer MAINTAINERS: Add include/dt-bindings/pwm to PWM SUBSYSTEM dt-bindings: pwm: mediatek: Add compatible string for MT8195 pwm: Add clock based PWM output driver dt-bindings: pwm: Document clk based PWM controller pwm: sifive: Shut down hardware only after pwmchip_remove() completed pwm: sifive: Ensure the clk is enabled exactly once per running PWM pwm: sifive: Simplify clk handling pwm: sifive: Enable clk only after period check in .apply() pwm: sifive: Reduce time the controller lock is held pwm: sifive: Fold pwm_sifive_enable() into its only caller pwm: sifive: Simplify offset calculation for PWMCMP registers pwm: mediatek: Add MT8365 support dt-bindings: pwm: Add MT8365 SoC binding pwm: Drop unused forward declaration from pwm.h pwm: Reorder header file to get rid of struct pwm_capture forward declaration pwm: atmel-tcb: Fix typo in comment ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pwm/clk-pwm.yaml46
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-mediatek.txt3
2 files changed, 49 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
new file mode 100644
index 000000000000..ec1768291503
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/clk-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock based PWM controller
+
+maintainers:
+ - Nikita Travkin <nikita@trvn.ru>
+
+description: |
+ Some systems have clocks that can be exposed to external devices.
+ (e.g. by muxing them to GPIO pins)
+ It's often possible to control duty-cycle of such clocks which makes them
+ suitable for generating PWM signal.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: clk-pwm
+
+ clocks:
+ description: Clock used to generate the signal.
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - clocks
+
+examples:
+ - |
+ pwm {
+ compatible = "clk-pwm";
+ #pwm-cells = <2>;
+ clocks = <&gcc 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_clk_flash_default>;
+ };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
index 033d1fc0f405..554c96b6d0c3 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
@@ -9,6 +9,8 @@ Required properties:
- "mediatek,mt7628-pwm": found on mt7628 SoC.
- "mediatek,mt7629-pwm": found on mt7629 SoC.
- "mediatek,mt8183-pwm": found on mt8183 SoC.
+ - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
+ - "mediatek,mt8365-pwm": found on mt8365 SoC.
- "mediatek,mt8516-pwm": found on mt8516 SoC.
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
@@ -18,6 +20,7 @@ Required properties:
has no clocks
- "top": the top clock generator
- "main": clock used by the PWM core
+ - "pwm1-3": the three per PWM clocks for mt8365
- "pwm1-8": the eight per PWM clocks for mt2712
- "pwm1-6": the six per PWM clocks for mt7622
- "pwm1-5": the five per PWM clocks for mt7623