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author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-04 18:44:38 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-04 18:44:38 -0700 |
commit | 31be1d0fbd950395701d9fd47d8fb1f99c996f61 (patch) | |
tree | a47055246206605177b455114203c7ccea9d0a50 /Documentation/devicetree/bindings/dma/fsl,edma.yaml | |
parent | 36001a2fa6cc63d58664a2a99b90a864f9eb587a (diff) | |
parent | a1873f837f9e5c1001462a635af1b0bab31aa9fd (diff) |
Merge tag 'dmaengine-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"New support / Core:
- Remove DMA_MEMCPY_SG for lack of users
- Tegra 234 dmaengine support
- Mediatek MT8365 dma support
- Apple ADMAC driver
Updates:
- Yaml conversion for ST-Ericsson DMA40 binding and Freescale edma
- rz-dmac updates and device_synchronize support
- Bunch of typo in comments fixes in drivers
- multithread support in sf-pdma driver"
* tag 'dmaengine-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (50 commits)
dmaengine: mediatek: mtk-hsdma: Fix typo 'the the' in comment
dmaengine: axi-dmac: check cache coherency register
dmaengine: sh: rz-dmac: Add device_synchronize callback
dmaengine: sprd: Cleanup in .remove() after pm_runtime_get_sync() failed
dmaengine: tegra: Add terminate() for Tegra234
dt-bindings: dmaengine: Add compatible for Tegra234
dmaengine: xilinx: use strscpy to replace strlcpy
dmaengine: imx-sdma: Add FIFO stride support for multi FIFO script
dmaengine: idxd: Correct IAX operation code names
dmaengine: imx-dma: Cast of_device_get_match_data() with (uintptr_t)
dmaengine: dw-axi-dmac: ignore interrupt if no descriptor
dmaengine: dw-axi-dmac: do not print NULL LLI during error
dmaengine: altera-msgdma: Fixed some inconsistent function name descriptions
dmaengine: imx-sdma: Add missing struct documentation
dmaengine: sf-pdma: Add multithread support for a DMA channel
dt-bindings: dma: dw-axi-dmac: extend the number of interrupts
dmaengine: dmatest: use strscpy to replace strlcpy
dmaengine: ste_dma40: fix typo in comment
dmaengine: jz4780: fix typo in comment
dmaengine: s3c24xx: fix typo in comment
...
Diffstat (limited to 'Documentation/devicetree/bindings/dma/fsl,edma.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/dma/fsl,edma.yaml | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml new file mode 100644 index 000000000000..050e6cd57727 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale enhanced Direct Memory Access(eDMA) Controller + +description: | + The eDMA channels have multiplex capability by programmable + memory-mapped registers. channels are split into two groups, called + DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed + by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,vf610-edma + - fsl,imx7ulp-edma + - items: + - const: fsl,ls1028a-edma + - const: fsl,vf610-edma + + reg: + minItems: 2 + maxItems: 3 + + interrupts: + minItems: 2 + maxItems: 17 + + interrupt-names: + minItems: 2 + maxItems: 17 + + "#dma-cells": + const: 2 + + dma-channels: + const: 32 + + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + big-endian: + description: | + If present registers and hardware scatter/gather descriptors of the + eDMA are implemented in big endian mode, otherwise in little mode. + type: boolean + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - dma-channels + +allOf: + - $ref: "dma-controller.yaml#" + - if: + properties: + compatible: + contains: + const: fsl,vf610-edma + then: + properties: + clock-names: + items: + - const: dmamux0 + - const: dmamux1 + interrupts: + maxItems: 2 + interrupt-names: + items: + - const: edma-tx + - const: edma-err + reg: + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: fsl,imx7ulp-edma + then: + properties: + clock-names: + items: + - const: dma + - const: dmamux0 + interrupts: + maxItems: 17 + reg: + maxItems: 2 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/vf610-clock.h> + + edma0: dma-controller@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>, + <0x40024000 0x1000>, + <0x40025000 0x1000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx7ulp-clock.h> + + edma1: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + /* last is eDMA2-ERR interrupt */ + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dma", "dmamux0"; + clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; + }; |