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| author | liuhongt <hongtao.liu@intel.com> | 2022-06-06 13:39:19 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-06-08 11:17:23 +0800 |
| commit | c45a9752f15bbc37d8efda0e29af5a2bfd53729d (patch) | |
| tree | 2081b83ec30b9b6bb229b37caefd22abc8c42a48 /libstdc++-v3/include/bits/basic_string.h | |
| parent | 1908e200078d88ffd3d4f834ff178a509482d750 (diff) | |
Fix insn does not satisfy its constraints: sse2_lshrv1ti3
21114(define_insn_and_split "ssse3_palignrdi"
21115 [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
21116 (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
21117 (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv")
21118 (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
21119 UNSPEC_PALIGNR))]
21120 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
which requires AVX512VL & AVX512BW for evex version.
gcc/ChangeLog:
PR target/105854
* config/i386/sse.md (ssse3_palignrdi): Change alternative 2
from Yv to Yw.
Diffstat (limited to 'libstdc++-v3/include/bits/basic_string.h')
0 files changed, 0 insertions, 0 deletions