diff options
| author | Andrew Pinski <apinski@marvell.com> | 2022-08-04 19:34:55 -0700 |
|---|---|---|
| committer | Andrew Pinski <apinski@marvell.com> | 2022-08-04 19:42:42 -0700 |
| commit | ffe4f55aa1bb18cc2793a4335450f34c33c9d01c (patch) | |
| tree | e0d953bfea94e1b420ef5c1bb390b2540441b6a7 | |
| parent | 4ad52740ba01f796c6c125aa2cc25115c3bf6693 (diff) | |
[RSIC-V] Fix 32bit riscv with zbs extension enabled
The problem here was a disconnect between splittable_const_int_operand
predicate and the function riscv_build_integer_1 for 32bits with zbs enabled.
The splittable_const_int_operand predicate had a check for TARGET_64BIT which
was not needed so this patch removed it.
Committed as obvious after a build for risc32-elf configured with --with-arch=rv32imac_zba_zbb_zbc_zbs.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/predicates.md (splittable_const_int_operand):
Remove the check for TARGET_64BIT for single bit const values.
| -rw-r--r-- | gcc/config/riscv/predicates.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 90db5dfcdd5..e98db2cb574 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -76,7 +76,7 @@ /* Check whether the constant can be loaded in a single instruction with zbs extensions. */ - if (TARGET_64BIT && TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op))) + if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op))) return false; /* Otherwise check whether the constant can be loaded in a single |